
88
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
8 External Memory Interface (EMI)
(continued)
8.5.5 Block Size Field Encoding
Table 63. Block Size Field
Encoding
8.5.6 Status Register
Table 64. Status Register
Value
0000
0001
0010
0011
0100
0101
0110
0111
Block Size (Bytes)
—
4 K
8 K
16 K
32 K
64 K
128 K
256 K
Address Bits to Match
Disabled
31:12
31:13
31:14
31:15
31:16
31:17
31:18
Value
1000
1001
1010
1011
1100
1101
1110
1111
Block Size (Bytes)
512 K
1 M
2 M
4 M
8 M
16 M
32 M
64 M
Address Bits to Match
31:19
31:20
31:21
31:22
31:23
31:24
31:25
31:26
Address 0xE000 3040
13
12
AE
PSWE
Bit #
Name
Bit #
31:16
15
31:16
RSVD
Name
RSVD
MACRE
15
14
11
10
9
8
7:0
MACRE
RSVD
RSVD
Description
PCAE
DCCRE
DCCWE
RSVD
Reserved.
MAC register error. This bit is set to 1 if an attempt is made to read/write the Ethernet MAC
registers in the 0xE001 0800:0xE001 FFFF range when the PHY is not active (i.e., when
the MAC is not receiving its
Tx/Rx
clocks).
Cleared by writing a 1 to this bit.
Reserved
.
Alignment error. This bit gets set to 1 if a nonaligned word access (with address bits 1:0
being nonzero) or a nonaligned half-word access (with address bit 0 being nonzero) is
attempted.
Cleared by writing a 1 to this bit.
Peripheral subword access error. If a half-word or byte access attempt is made to the
peripheral address space (0xE000 0000:0xEFFF FFFF).
Cleared by writing a 1 to this bit.
Reserved
.
Peripheral code access error.
This bit gets set to 1 if an opcode fetch is attempted from
peripheral address space (0xE000 0000:0xEFFF FFFF).
Cleared by writing a 1 to this bit.
DCC read error. This bit gets set to 1 if the
ARM
processor/DMA controller attempts to read
from the
ARM
2DSP data buffer (0xE004 0000:0xE004 07FF).
Cleared by writing a 1.
14
13
RSVD
AE
12
PSWE
11
10
RSVD
PCAE
9
DCCRE