18
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
2 Pinout Information
(continued)
2.2 Pin List
Table 1. PBGA-272 Package
Ball
Signal
Description
I/O
Pull-Up/Down
Source/Sink
Current
ARM
to DSP Communications Interface
DSP interface address bus bit 0 (LSB)
DSP interface address bus bit 1
DSP interface address bus bit 2
DSP interface address bus bit 3
DSP interface address bus bit 4
DSP interface address bus bit 5
DSP interface address bus bit 6
DSP interface address bus bit 7
DSP interface address bus bit 8
DSP interface address bus bit 9
DSP interface address bus bit 10 (MSB)
DSP interface data bus bit 0 (LSB)
DSP interface data bus bit 1
DSP interface data bus bit 2
DSP interface data bus bit 3
DSP interface data bus bit 4
DSP interface data bus bit 5
DSP interface data bus bit 6
DSP interface data bus bit 7
DSP interface data bus bit 8
DSP interface data bus bit 9
DSP interface data bus bit 10
DSP interface data bus bit 11
DSP interface data bus bit 12
DSP interface data bus bit 13
DSP interface data bus bit 14
DSP interface data bus bit 15 (MSB)
Read high write low memory signal
Chip select interprocessor memory
Chip select interprocessor semaphores and interrupt
DSP interrupt
Crystal for Main Clock and Real-Time Clock
Input pin to connect 32.768 kHz crystal
Output pin to connect 32.768 kHz crystal
Output pin to connect 11.52 MHz crystal
Input pin to connect 11.52 MHz crystal
Test mode clock input
Reset output
H1
J4
J3
J2
J1
K2
K3
K1
L1
L2
L3
B1
C2
D2
D3
E4
C1
D1
E3
E2
E1
F3
G4
F2
F1
G3
G2
G1
H3
H2
L4
DSP_A[0]
DSP_A[1]
DSP_A[2]
DSP_A[3]
DSP_A[4]
DSP_A[5]
DSP_A[6]
DSP_A[7]
DSP_A[8]
DSP_A[9]
DSP_A[10]
DSP_D[0]
DSP_D[1]
DSP_D[2]
DSP_D[3]
DSP_D[4]
DSP_D[5]
DSP_D[6]
DSP_D[7]
DSP_D[8]
DSP_D[9]
DSP_D[10]
DSP_D[11]
DSP_D[12]
DSP_D[13]
DSP_D[14]
DSP_D[15]
DSP_RWN
DSP_MCSN
DSP_ICSN
DSP_INTN0
I
I
I
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
—
—
—
—
P4
T1
T4
V1
M1
N2
XRTC0
XRTC1
XTAL0
XTAL1
TSTCLK
RTS0N
I
—
—
—
—
—
—
—
—
—
—
O
O
I
O
O
4 ma/4 ma
4 ma/4 ma