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| 型號： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁數(shù)： | 215/248頁 |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
213
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
15 Synchronous Serial Interface (SSI)
(continued)
If
the
SSN
signal is asserted by another master some considerable time after
the master
enables its
SCK
and
MDOSDI
drivers,
the following events occur:
I
The SSI is disabled. The
EN
bit of
SSI control register 1
is set to 0.
I
The SSI is reconfigured as a slave. The
MSTR
and
SDONE
bits are cleared to 0.
I
The master data output is disabled.
I
The
SCK
output pin is disabled.
I
MODF
flag of
SSI interrupt register
is set to 1.
Note:
The
MDOEN
bit of
SSI control register 1
remains set although this is harmless, since the SSI is reconfig-
ured as a slave after the mode fault so the
MDOEN
bit has no effect.
The
MODF
interrupt
is asserted if
MODFE
is enabled in the
SSI interrupt enable register
. If the
FASTCLEAR
bit
of
SSI control register 2
is 1, the
MODF
flag is cleared by
a read/write of the SSI data register
. If the
FASTCLEAR
bit of
SSI control register 2
is zero, the
MODF
flag is cleared by writing a 1 to the
SSI interrupt register’s
MODF
.
15.3.6.4 RD_ORUN
If the SSI is configured as a master, a read overrun error can occur if the
RD_ORUN
bit is set in the
SSI interrupt
enable register
. The
RD_ORUN
bit in
SSI interrupt register
indicates the error. If
RD_ORUN
is 1 and the SSI is
a master, a read overrun error occurs when the master’s
SSI data register
is overwritten with new data from the
slave before the prior data from the slave is read from the register. The
SSI data register
is written with new data
from the slave at the end of each byte transfer.
It is anticipated that the read overrun error will be enabled (i.e.,
RD_ORUN
will be 1) only when the DMA is being
used to transfer data from the
SSI data register
to memory. A read overrun error can occur when the firmware
writes a new data byte (e.g., byte number 2) to the
SSI data register
(that starts a new transfer) before the DMA
reads the byte (e.g., byte number 1) previously received from the slave.
The
SSI data register
is double-buffered on the read side, so byte number 1 is not overwritten in the
SSI data reg-
ister
with the new data received from the slave (byte number 3) until the end of the transfer of byte number 2. This
means that in order to avoid a read overrun error, the DMA must read byte number 1 from the
SSI data register
before the transfer of byte number 2 is complete.
If a read overrun error does occur, the
RD_ORUN
bit will be set in
SSI interrupt register
and an interrupt will be
generated from the SSI. The
RD_ORUN
bit and the interrupt are automatically cleared by writing a 1 to the
RD_ORUN
field in
the SSI interrupt register
.
15.3.7 SSI Transfer Abort
An ongoing transfer to a slave is aborted by the master by deasserting the
SSN
signal to the slave or by the slave
software writing a 0 to
SSI control register 1
bit 10 in the slave. If the SSI is configured as a slave and the
SSN
line is pulled high, or
SSI control register 1
bit 10 goes to 0 during transmission, all counters are reset. The state
of the
SSI data register
is frozen at the time of the occurrence of the error. New data has to be written to the
slave’s
SSI data register
to have a meaningful transmission following the error. There are no flags to indicate an
aborted transfer. This condition is detected by software protocol.
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相關(guān)代理商/技術(shù)參數(shù) |
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| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302B | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302F | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303ABNAD | 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light) |
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