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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 168/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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166
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
13 USB Host Controller
(continued)
13.3.3 Hc Command Status Register
The
Hc command status register
is used by the host controller to receive commands issued by the host controller
driver, as well as reflecting the current status of the host controller. To the host controller driver, it appears to be a
write to set the register. The host controller must ensure that bits written as 1 become set in the register, while bits
written as 0 remain unchanged in the register. The host controller driver may issue multiple distinct commands to
the host controller without concern for corrupting previously issued commands. The host controller driver has nor-
mal read access to all bits.
The
SOC
field indicates the number of frames with that the host controller has detected the scheduling overrun
error. This occurs when the periodic list does not complete before end of frame. When a scheduling overrun error is
detected, the host controller increments the counter and sets the scheduling overrun field in the
Hc interrupt sta-
tus register
(see Table 148 on page 167)
.
Table 147
.
Hc Command Status
Register
Address 0xE000 7008
15:4
RSVD
Read/Write
HCD
HC
—
—
Reserved.
R
R/W
Scheduling overrun count. These bits are incremented on
each scheduling overrun error. It is initialized to 00b and
wraps around at 11b. This will be incremented when a sched-
uling overrun is detected even if scheduling overrun in
Hc
interrupt status register
(see Table 148 on page 167)
has
already been set. This is used by HCD to monitor any persis-
tent scheduling problems.
—
—
Reserved.
R/W
R/W
Ownership change request. This bit is set by an OS HCD to
request a change of control of the HC. When set, HC will set
the ownership change field in the
Hc interrupt status regis-
ter
. After the changeover, this bit is cleared and remains so
until the next request from OS HCD.
R/W
R/W
Bulk list filled. This bit is used to indicate whether there are
any TDs on the bulk list. It is set by HCD whenever it adds a
TD to an ED in the bulk list. When HC begins to process the
head of the bulk list, it checks
BLF
. As long as
BLF
is 0, HC
will not start processing the bulk list. If
BLF
is 1, HC will start
processing the bulk list and will set
BLF
to 0. If HC finds a TD
on the list, then HC will set
BLF
to 1, causing the bulk list pro-
cessing to continue. If no TD is found on the bulk list, and if
HCD does not set
BLF
, then
BLF
will still be 0 when HC com-
pletes processing the bulk list and bulk list processing will
stop.
Bit #
Name
Bit #
31:18
RSVD
Key
17:16
SOC
Reset
3
2
1
0
OCR
BLF
CLF
HCR
Description
31:18
17:16
RSVD
SOC
—
00b
15:4
3
RSVD
OCR
—
0b
2
BLF
0b
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