參數(shù)資料
型號(hào): T8302
英文描述: T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q
中文描述: T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)(ARM)的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量
文件頁(yè)數(shù): 229/248頁(yè)
文件大?。?/td> 7321K
代理商: T8302
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Agere Systems Inc.
227
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
17 Key and Lamp Controller (KLC)
(continued)
The seven row output pins are driven by an 8 mA type output driver. This will provide a minimum low-
level
current
output of 8 mA and a minimum high-
level
current output of 8 mA. The 8 column output pins are driven by a 4 mA
type output driver. This will provide a minimum low-level output current of 4 mA and a minimum
high-level
output
current of 4 mA. Each column output pin also contains a 50 K
pull-down resistor. The
LCNTRL
output pin is
driven by a 8 mA type output driver. This will provide a minimum low-
level
current output of 8 mA and a minimum
high-
level
current output drive of 8.0 mA. The message and speaker LED output pins are driven by an 8 mA type
output driver. This will provide a minimum low-
level
current output of 8 mA and a minimum high-
level
current output
of 8 mA.
The seven row output pins
K_ROW[6:0]
are driven active-low one at a time, each turning on a single row in the
LED drive matrix. The other rows are 3-stated to turn off the respective transistor, disabling that row's power.
Spe-
cific LEDs in the enabled row are turned on by driving the corresponding column pins active-high.
LCNTRL
is
driven active-high to enable the entire LED drive matrix.
The seven row output pins
K_ROW[6:0]
are driven active-high to sample the key scan matrix. The column pins are
3-stated during the key scan process but their pull-down resistor will keep them at a low logic level unless a key is
depressed and that column pin is pulled high by the low impedance path created between that key's row and col-
umn pins.
The message and speaker LEDs are connected to the
MSGLED
and
SPKRLED
pins. These pins are driven
active-low to turn on the respective LEDs. These pins will also be driven active-low when the KLC is in a software
or hardware reset state. This will enable a user to detect the presence of power on the set if the microprocessor is
not working properly. These LEDs will be off after the KLC exits the reset state and each LED will be controlled by
its
lamp rate register
.
17.3 KLC Register
17.3.1 Lamp Rate Registers
Rate generation for the LED key matrix is provided by the
lamp rate register
for address
0xE000 D000:0xE000 D06C. In addition, one more register is provided (0xE000 D070) for programming rate gen-
eration to the speaker and message LEDs. There are 56 LEDs; one register for two LEDs.
Pin Name
K_COL[7:0]
I/O Type
I/O
Current IOH
4 mA
Current IOL
4 mA
Pull-up/Down
50K pull-down
I/O Signal Description
8 column input/output for LED drive
matrix and inputs for key scan
matrix.
Message and speaker LED direct
output. Active-low.
MSGLED,
SPKRLED
SWHOOK
O
8 mA
8 mA
None
I
Table 199. KLC Register Map
Register
Address
Lamp rate registers
Noscan control register
Key scan status register
KLC interrupt register
KLC interrupt enable register
0xE000 D000:0xE000 D070
0xE000 D100
0xE000 D140
0xE000 D180
0xE000 D1C0
Table 198. KLC Matrix Pins
(continued)
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