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參數(shù)資料
| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 13/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Table of Contents
(continued)
Tables
Page
Agere Systems Inc.
11
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Table 51. Timer Interrupt Mask Register ................................................................................................................76
Table 52. Timer Control Register ...........................................................................................................................76
Table 53. IT Count Registers ..................................................................................................................................77
Table 54. IPT_
ARM
Processor Memory Map .........................................................................................................78
Table 55. EMI FLASH/SRAM Read Access Timing Parameters ............................................................................81
Table 56. EMI FLASH/SRAM Write Access Timing Parameters ............................................................................82
Table 57. EMI FLASH Register Map ......................................................................................................................84
Table 58. Chip Select Configuration Register FLASH_CS .....................................................................................84
Table 59. Chip Select Configuration Registers CS1, CS2, CS3 .............................................................................85
Table 60. Hold States Encoding .............................................................................................................................87
Table 61. Wait-States Encoding .............................................................................................................................87
Table 62. Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM ..............................87
Table 63. Block Size Field Encoding ......................................................................................................................88
Table 64. Status Register .......................................................................................................................................88
Table 65. Options Register .....................................................................................................................................89
Table 66. External SDRAM Memory Map ..............................................................................................................89
Table 67. SDRAM Memory Range Base Address Register ...................................................................................90
Table 68. SDRAM Control Register ........................................................................................................................90
Table 69. SDRAM Timing and Configuration Register ...........................................................................................90
Table 70. SDRAM Manual Access Register ...........................................................................................................91
Table 71. SDRAM Access Cycles, Using a 64 Mbit SDRAM .................................................................................95
Table 72.
ARM
Processor Memory and I/O Map ....................................................................................................96
Table 73. Token Register .......................................................................................................................................97
Table 74. DSP2
ARM
Interrupt Register ................................................................................................................98
Table 75.
ARM
2DSP Interrupt Register ................................................................................................................98
Table 76. DCC Controller I/O Signals .....................................................................................................................99
Table 77. MAC Register Map ...............................................................................................................................105
Table 78. MAC Controller Setup Register ............................................................................................................106
Table 79. MAC Packet Delay Alarm Value Register ............................................................................................108
Table 80. MAC Controller Interrupt Enable Register ............................................................................................108
Table 81. MAC Control Frame Destination Address Registers ............................................................................109
Table 82. MAC Control Frame Source Address Registers ...................................................................................109
Table 83. MAC Control Frame Length/Type Register ..........................................................................................110
Table 84. MAC Control Frame Opcode Register ..................................................................................................110
Table 85. MAC Control Frame Data Register .......................................................................................................111
Table 86. VLAN Type1 Type/Length Field Register .............................................................................................111
Table 87. VLAN Type2 Type/Length Field Register .............................................................................................111
Table 88. MAC Transmit FIFO Register ...............................................................................................................111
Table 89. MAC Receive FIFO Register ................................................................................................................112
Table 90. MAC Receive Control FIFO Register ...................................................................................................112
Table 91. MDIO Address Register ........................................................................................................................114
Table 92. MDIO Data Register .............................................................................................................................114
Table 93. MAC PHY Powerdown Register ...........................................................................................................115
Table 94. MAC Controller Transmit Control Register ...........................................................................................115
Table 95. MAC Controller Transmit Start Register ...............................................................................................116
Table 96. MAC Transmit Status Register .............................................................................................................116
Table 97. MAC Collision Counter .........................................................................................................................118
Table 98. MAC Packet Delay Counter ..................................................................................................................118
Table 99. MAC Transmitted Packet Counter ........................................................................................................118
Table 100. MAC Transmitted Single Collision Counter ........................................................................................118
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