參數(shù)資料
型號(hào)： T8302
英文描述： T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q
中文描述： T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量
文件頁(yè)數(shù)： 203/248頁(yè)
文件大小： 7321K
代理商： T8302
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Agere Systems Inc.
201
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
15 Synchronous Serial Interface (SSI)
(continued)
The 8-bit data register shifts out a byte, one bit at a time (MSB first), synchronously with the shift clock
SCK
. If run-
ning as a master, the SSI derives
SCK
from its system clock using a prescaling value determined by the
SCLK[2:0]
bits of
SSI control register 1
(see Table 183 on page 204)
. Before being output to the pin, the pre-
scaled clock is conditioned in the clock control block in accordance with the
SPOL
and
SPHA
bits in
SSI control
register 1
. As a slave, the shift clock is supplied by an external master through the
SCK
pin and is modified in
accordance with the
SPOL
and
SPHA
bits in the slave’s
SSI control register 1
.
15.1.2 Date Transfer
The
data register
loads data from the lower byte of the peripheral bus. The received data is double buffered and is
read on the lower byte of the peripheral bus.
The status and shift control logic directs the transfer of data and generates status flags for end-of-transfer
(
SDONE
) and detectable error conditions (
WCOLL
and
MODF
). The bits from the
SSI control registers
are used
by the clock divide, clock control, status/shift/control, and the I/O control logic for proper operation.
The I/O control logic routes the data to and from the I/O pins as shown below.
15.1.3 Pin Configuration
Because a master
MDISDO
is the data input,
MDOSDI
is the data output and
SCK
is the serial clock output.
SSN
is the slave select signal and is always an input to the SSI unit, whether the unit is a master or a slave. If a master,
the
SSN
input pin detects bus contention with another master in a multimaster system.
Because a slave
MDISDO
is the data output,
MDOSDI
is the data input,
SCK
is the serial clock input, and
SSN
is
the slave select input. The I/O control logic is directly controlled by the
MSTR
bit of
SSI control register 1
.
15.1.4 SSN Input
If
SSN
is low in a slave unit, the slave SSI is selected by the master for operation. If low in a master unit, this pin
indicates that there is contention with another master in the system, and this will be detected as a mode fault error
if
SSNEN
of
SSI control register 1
is set to 1. The
SSN
pin is used by the SSI hardware (as long as
SSNEN
of
SSI control register 1
is one) but can also be read by master or slave software from
SSN
of
SSI control
register 2
. Bit 0 of
SSI control register 2
reflects the state of the
SSN
pin, regardless of the state of
SSNEN
of
SSI control register 1
.
15.1.5 Configurations
Multimaster: in a multiple-master system, all
SCK
pins are tied together, all
MDOSDI
pins are tied together, and all
MDISDO
pins are tied together.
Master—slave: a single SSI device is configured as a master and all other SSI devices on the SSI bus are config-
ured as slaves. The master drives data onto its
SCK
and
MDOSDI
pins to the
SCK
and
MDOSDI
pins of the
slaves.
The slave, whose
SSN
input pin is low, optionally drives data out onto its
MDISDO
pin to the
MDISDO
pin of the
master. The
SCK, MDOSDI
, and
MDISDO
pins are configured to behave as open-drain drivers using bits in
SSI
control register 1
. This prevents contention on these signals if more than one SSI device tries to simultaneously
drive the line. An external pull-up resistor is required on all open-drain pins.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T8302A 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die
T8302B 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die
T8302F 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die
T8303A 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die
T8303ABNAD 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light)
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