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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 61/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
59
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
6 Programmable Direct Memory Access (DMA) Controller
(continued)
I
Or, the DMA will transfer indefinitely in circular buffer mode until software resets the DMA start bit (
CS
) in the
DMA control register
(see Table 36 on page 62)
. In circular buffer mode, the transfer will continue as data
becomes available from the peripheral as indicated by the DMA ready signal from the peripheral. Circular buffer
mode is selected by setting the
CBM
bit in the
DMA control register
(see Table 36 on page 62)
to 1.
CBM Operation:
I
The buffer size is set by writing to the
DMA preload transfer count register
(see Table 40 on page 65)
.
I
The DMA will then transfer data to the memory as data becomes available from the peripheral until the transfer
count
TCNT
(
see Table 41 on page 65
) is reached.
I
The
DMA destination address register
(see Table 39 on page 64)
and the
DMA transfer count register
(see
Table 41 on page 65)
will then be rewritten with the preset values stored in their respective
preload registers
.
I
The circular buffer reload counter (
PCNTx
) in the
DMA status register
(see Table 43 on page 66)
will be incre-
mented whenever the transfer loops back to the preset values.
I
This DMA is gated by the DMA ready signal from the peripheral selected for the transfer. If the DMA ready signal
is deasserted before the number of words programmed into the
DMA burst and hold count register
(see Table
42 on page 66)
, the burst will halt and the DMA will relinquish the bus for the programmed number of hold states
before it will monitor the DMA ready signal again. When the DMA ready signal is reasserted the DMA will
request the bus, and will transfer up to burst count again when it receives its bus grant.
There is a software controlled DMA mode that does not use the DMA ready signal from the peripheral. This mode
is selected by setting the software trigger enable bit (
SDRQ_E
) in the
DMA control register
(see Table 36 on page
62)
. When the user is sure the number of words set up to be transferred is available in the peripheral's buffer, the
DMA is triggered by setting the software trigger DMA request bit (
SDRQ
) in the
DMA control register
(see Table
36 on page 62)
.The DMA ready signal is not monitored in this mode. If the DMA attempts to transfer more data
than can be buffered in the peripheral, data will be lost and questionable results will occur.
Notes:
Data transfers to memory from the DSP2
ARM/ARM
2DSP buffer in the DCC block are much more efficient
in this mode, using the peripheral bus address of the DSP2
ARM/ARM
2DSP buffer, as opposed to using
the memory-to-memory mode (mode 0) and the system bus address of the DSP2
ARM/ARM
2DSP buffer.
The memory write and buffer read can occur at the same time since they are on different busses in the
IPT_
ARM
, instead of the sequential read-then-write, that occur in the memory-to-memory mode.
6.1.4 Mode 2. Memory-to-Peripheral in Blocks of Burst Count Size
DMA mode 2 (memory-to-peripheral) is selected by setting
CMODE[2:0]
of the
DMA control register
(see Table
36 on page 62)
to 010.
Memory-to-peripheral transfers are set up as specified in
6.1.1 DMA Transfer Setup Procedure
.
I
In general, all transfers to/from peripherals should be 32-bit transfers and valid data should be written into or
read from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer
size. The supported peripherals for DMA are Ethernet, SSI, IrDA, and UART. The
ARM
2DSP and DSP2
ARM
buffers may also be treated as peripherals while using the software triggered DMA
mode (
see Section 6.1.4.1 on
page 60
).
I
When the start bit (
CS
) in the
DMA control register
(see Table 36 on page 62)
is set to 1, the DMA transfer will
start immediately in memory-to-peripheral mode (mode 2) as soon as the DMA ready signal is asserted. In the
mixed memory peripheral modes (modes 1 and 2), a software trigger (
SDRQ
) can be used to force the DMA to
see DMA ready. The DCC block does not supply a DMA ready signal to trigger the DMA transfers so the
software-triggered DMA mode must always be used for these transfers.
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