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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 123/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
121
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
10 Ethernet 10/100 MAC
(continued)
Table 106. MAC Controller Interrupt Status Register
(continued)
Warning:
ARM
accesses to the MAC registers within the address space 0xE001 0800—0xE001 FFFF when
both Ethernet ports are down or when the repeater is disabled will generate an
ARM
data abort.
The abort occurs because this register space requires clocks that are only present if link is
achieved or if the repeater is used. If these registers must be accessed prior to achieving link on
the Ethernet ports, the repeater should first be enabled.
10.8 Signal Information
10.8.1 MII MAC I/O Signals
Bit #
6
5*
4*
3*
2*
1*
0*
Name
RSVD
TPLI
ECI
LCI
EXDEFI
EXCOLI
DFUND
Description
Reserved.
Packet late interrupt.
Transmit packet late interrupt.
Early collision detect.
Early collision detect interrupt.
Late collision.
Late collision detect interrupt.
Excess deferral.
Excess deferral interrupt.
Excess collision.
Excess collision interrupt.
FIFO data underrun.
Transmit data FIFO data underrun interrupt.
* Read-only latch, (ROL). A read-only latch is similar to a read-only (RO) field, except that once it is set, it stays set regardless of the state of
any event that set it in the first place. It can only be reset by the microprocessor writing a
1
to the bit. Note that the microprocessor writing a
0
to a ROL has no effect at all.
Table 107. MII MAC I/O Signals
Signal
COL
Type
I
Description
Collision.
Used to indicate a collision between two stations. Assumed to be active for a mini-
mum of two
TX_CLK
cycles.
COL
is
sampled during half-duplex transmit operations when
TXE
is active.
Carrier sense.
Asynchronously asserted by the physical layer when traffic is detected on the
medium.
Receive clock. Receive clock operates at 2.5 MHz or 25 MHz.
RX_CLK
is sourced by the
physical layer device.
Receive data. 4-bit nibble containing received data.
RXD
is valid on the rising edge of
RX_CLK.
Receive data valid.
Used to indicate that the data on
RXD
is valid.
Receive error.
Asserted by the PHY when it has detected an error with the frame currently
being received.
Transmit clock. 2.5 MHz or 25 MHz 50% duty cycle, continuously running.
TX_CLK
clocks all
transmitter and timer logic.
Transmit data. 4-bit nibble with data to be transmitted.
Transmit error. Indicates a transmit error.
Transmit enable.
Indicates that the data on the
TXD[3:0]
lines is valid.
Management data clock. This is a 2.5 MHz (maximum) clock to exchange management data
with a device on
MDIO
.
Management data.
This is bidirectional management data for an external device.
CRS
I
RX_CLK
I
RXD[3:0]
I
RX_DV
RX_ERR
I
I
TX_CLK
I
TXD[3:0]
TX_ERR
TX_EN
MDC
O
O
O
O
MDIO
BI
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