132
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.4.4 Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B
Table 112. Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B
Signal
MIITXD[3:0]
Type
I
Description
MII transmit data.
In 10 Mbits/s mode,
MIITXD [3:0]
represents the 4-bit data to be transmitted by the
repeater.
MIITX_EN
must be asserted when data is to be transferred.
MRTXD
is
clocked into the repeater slice with
MIICLK
.
In 100 Mbits/s mode,
MIITXD [3:0]
represents the 4-bit data to be transmitted by the
repeater.
MIITX_EN
must be asserted when data is to be transferred.
MIITXD
is
clocked into the backplane segment with MIICLK.
MII transmit enable.
MIITX_EN
I
In 10 Mbits/s mode (segment B only),
MIITX_EN
indicates the MAC is presenting nib-
bles on the MII for transmissions.
MIITX_EN
must be asserted synchronously with the
first nibble of the preamble and remain asserted while all nibbles to be transmitted are
presented to the MII.
MIITX_EN
must be deasserted prior to the first
MIICLK
following
the final nibble of a frame.
MIITX_EN
is clocked into the backplane segment with the ris-
ing edge of
MIICLK
.
In 100 Mbits/s mode,
MIITX_EN
indicates the MAC is presenting nibbles on the MII for
transmission.
MIITX_EN
must be asserted synchronously with the first nibble of the
preamble and remain asserted while all nibbles to be transmitted are presented to the
MIITX_EN.
MIITX_EN
must be deasserted prior to the first
MIICLK
following the final
nibble of a frame.
MIITX_EN
is clocked into the backplane segment with the rising edge
of
MIICLK
.
MII transmit error.
MIITX_ER
I
In 10 Mbits/s mode,
MIITX_ER
is not monitored.
In 100 Mbits/s mode,
MIITX_ER
indicates the MAC is requesting that the repeater
transmit a coding error.
MIITX_ER
will be clocked with the rising edge of
MIICLK
.
MII transmit/receive clock.
MIICLK
O
In 10 Mbits/s mode, the 2.5 MHz clock is used to transfer nibble data to or from the
MAC.
In 100 Mbits/s mode, the 25 MHz clock is used to transfer data to or from the MAC.
Receive data.
MIIRXD[3:0]
O
In 10 Mbits/s mode and in 100 Mbits/s mode,
MIIRXD [3:0]
represents the 4-bit data
being sent to the MAC.
MIIRX_DV
will be asserted when data is to be accepted by the
MAC.
MIRXD
is clocked out of the backplane segment with the falling edge of
MIICLK
.
MIIRXD [0]
is the least significant bit of the nibble.