
20
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
2 Pinout Information
(continued)
Ball
Signal
Description
I/O
Pull-Up/Down
Source/Sink
Current
Common External Memory Interface
(continued)
EMI address bus bit 17
EMI address bus bit 16
EMI address bus bit 15
EMI address bus bit 14
EMI address bus bit 13
EMI address bus bit 12
EMI address bus bit 11
EMI address bus bit 10
EMI address bus bit 9
EMI address bus bit 8
EMI address bus bit 7
EMI address bus bit 6
EMI address bus bit 5
EMI address bus bit 4
EMI address bus bit 3
EMI address bus bit 2
EMI address bus bit 1
EMI address bus bit 0 (LSB)
USB Interface
Bidirectional port power
Input port power fault
Bidirectional differential USB port signal
Bidirectional differential USB port signal
Universal serial bus alternate clock
Synchronous Serial Interface
Master data output, slave data input
Master data input, slave data output
Synchronous serial select
Clock signal
Parallel Port Interface
Parallel peripheral interface bit 15
Parallel peripheral interface bit 14
Parallel peripheral interface bit 13
Parallel peripheral interface bit 12
Parallel peripheral interface bit 11
Parallel peripheral interface bit 10
Parallel peripheral interface bit 9
Parallel peripheral interface bit 8
Parallel peripheral interface bit 7
Parallel peripheral interface bit 6
A17
C16
B16
A16
C15
D14
B15
A15
C14
B14
A14
C13
B13
A13
D12
C12
B12
A12
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
E18
D19
E17
D18
Y1
PRTPWR
PWRFLTN
DPLS
DMNS
USBALTCK
I/O
*
I
I/O
I/O
I
*
—
4 ma/4 ma
—
—
—
4 ma/4 ma
50 k
pull-up
—
—
50 k
pull-up
W1
V3
W2
V2
MDOSDI
MDISDO
SSN
SCK
I/O
*
I/O
*
I/O
*
I/O
*
50 k
pull-up
—
—
—
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
J19
J18
J17
H20
H19
H18
G20
G19
F20
G18
PPI[15]
PPI[14]
PPI[13]
PPI[12]
PPI[11]
PPI[10]
PPI[9]
PPI[8]
PPI[7]
PPI[6]
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
I/O
*
—
—
—
—
—
—
—
—
—
—
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
4 ma/4 ma
*Schmitt trigger input.
Table 1. PBGA-272 Package
(continued)