
156
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
12 Ethernet 10/100 PHY(s)
(continued)
12.5.16 MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description
Bit #
3
Name
RXERR_ST
Type
R/LH*
Description
RX error status.
Indicates a false carrier. This bit will latch high until read.
This bit is only valid in 100 Mbits/s mode.
Force jam. This bit will latch high until read.
2
FRC_JAM
R/LH*
This bit is only valid in 100 Mbits/s mode.
Link up 100. When this bit is set to a 1, it indicates that a 100 Mbits/s trans-
ceiver is up and operational.
Link up 10.
When this bit is set to a 1, it indicates that a 10 Mbits/s trans-
ceiver is up and operational.
1
LNK100UP
R
0
LNK10UP
R
* LH = latched high.
Table 141. MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description
Bit #
15
Name
LOCALRST
Type
R/W
Description
Management reset.
This is the local management reset bit. Writing a
logic 1 to this bit will cause the lower 16 registers and
registers MR28
and
MR29
to be reset to their default values.
This bit is self-clearing.
Generic reset 1.
This register is used for manufacture test only.
Generic reset 2. This register is used for manufacture test only.
100 Mbits/s transmitter off.
14
13
12
RST1
RST2
100_OFF
R/W
R/W
R/W
If set to 0, it forces
TPI
low and
TPIN
high. Default = 1.
Reserved.
11
RSVD
R/W
Default = 0.
Carrier sense select.
MCRS
will be asserted on receive only when this
bit is set to a 1. If this bit is set to logic 0,
MCRS
will be asserted on
receive or transmit. This bit should be set to one when the repeater is
used, and cleared to zero when the repeater is bypassed.
10
CRS_SEL
R/W
This bit is ORed with the
CRS_SEL
pin.
Link error indication.
9
LINK_ERR
R/W
If 1, a link error code will be reported on
MRXD[3:0]
of the
10/100 Ethernet transceiver macrocell when
MRX_ER
is asserted on
the MII. The specific error codes are listed in the
MRXD
pin description.
If it is 0, it will disable this function.
Packet error indication enable.
8
PKT_ERR
R/W
If 1, a packet error code, that indicates that the scrambler is not locked,
will be reported on
MRXD[3:0]
of the 10/100 Ethernet transceiver mac-
rocell when
MRX_ER
is asserted on the MII.
If 0, it will disable this function.
Table 140. MR28 Device-Specific Register 1 (Status Register) Bit Description
(continued)