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| 型號： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁數(shù)： | 99/248頁 |
| 文件大小： | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
97
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
9 DSP Communications Controller (DCC)
(continued)
9.2 DCC Token Register
The DSP communications controller (DCC) provides a 16-bit
token register
(see Table 73 on page 97)
. The upper
byte (
DSPT
) of this register is writable only through the DSP interface. The lower byte (
ARM
T
) of this register is
writable only through the
ARM
APB bus. The entire 16-bit
token register
can be read by either interface.
The
token register
should help the programmer manage the communication buffers. A jitter buffer, for example,
can be implemented by using the token bits to mark full areas and empty sections of the buffer. When an audio
packet is placed in the buffer by the IPT_
ARM
, it could interrupt the DSP with information about the section where
this packet was placed. The DSP could then use one of its token bits to mark that section as full. At the appropriate
time, the DSP could then remove a packet that was placed in its buffer many milliseconds earlier and mark this
other section as empty.
Table 73. Token Register
9.3 DCC Interrupt Registers
There are two
DCC
interrupt registers
in the IPT_
ARM
. The
DSP2
ARM
interrupt register
(see Table 74 on page
98)
is used by an external device (the IPT_DSP) to generate an interrupt to the
ARM
940T processor core. The
ARM
2DSP interrupt register
(see Table 75 on page 98)
is written by the
ARM
940T processor to generate an
active-low interrupt output. This interrupt output is to be connected to the IPT_DSP interrupt input (
DSP_INT0
).
Both of these registers are similarly organized. Bit 15, the MSB, is the interrupt bit and can only be written to 1 by
the interrupting processor. Bit 15 (
DSP2
ARM
_INT)
in the
DSP2
ARM
interrupt register
can only be set by the
external DSP through the DCC interface. Bit 15 (
ARM
2DSP_INT
) in the
ARM
2DSP interrupt register
can only
be set by the IPT_
ARM
processor.
DSP2
ARM
_INT
and
ARM
2DSP_INT
can read by both processors.
When bit 15 is set to 1 by the appropriate processor,
INT_CLR
and
INT_FLAG
are automatically set to 1. These
bits can only be written to 0 by the interrupted processor. When the interrupted processor writes
INT_CLR
to 0, bit
15 is automatically reset to 0 and clears the interrupt. In addition the interrupted processor can write
INT_FLAG
to
0 to indicate that it has completed the operation, or freed up the memory.
Bits 12:0 (
INT_MSG
) of the
ARM
2DSP interrupt register
(see Table 75 on page 98)
can only be written by the
interrupting processor, which uses these bits to implement a message-passing protocol to signal the purpose of
the interrupt. These bits can also be used to identify an offset and length in the interprocessor communication buff-
ers where a message, or data, is stored.
This message-interrupt scheme should help the programmers pass data and commands back and forth while pre-
venting a processor from overwriting a set of data in the interprocessor communications buffer before the other
processor has finished accessing it.
Address 0xE000 F000
Bit #
Name
Bit #
31:16
15:8
31:16
RSVD
15:8
DSPT
Description
7:0
ARM
T
Name
RSVD
DSPT
Reserved.
DSP writable token bits. These bits can only be written through the DSP interface but
they are readable by both the DSP and the
ARM
.
ARM
writable token bit. These bits can only be written by the
ARM
processor but they are
readable by both the DSP and the
ARM
.
7:0
ARM
T
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