Agere Systems Inc.
57
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
6 Programmable Direct Memory Access (DMA) Controller
(continued)
6.1.1 DMA Transfer Setup Procedure
All DMA transfers are set up by doing the following:
I
Program the source address through the
DMA
source address register
(see Table 37 on page 64)
. This is the
beginning address where the DMA controller will start the transfer.
I
Program the destination address through the
DMA
preload destination start address register
(see Table 38
on page 64)
. This is the beginning address where the source data will be transferred.
I
Program the transfer count through the
DMA
preload transfer count register
(see Table 40 on page 65)
.
I
Program the burst size and number of hold states in the
DMA
burst and hold count register
(see Table 42 on
page 66)
. The DMA releases the bus to allow other masters access to it after each burst by the number of hold
states programmed in the
DMA
burst and hold count register
.
I
Program the appropriate control codes into the
DMA control register
(see Table 36 on page 62)
. This includes
setting the following:
— Peripheral select (
PS
)—selects Ethernet, IrDA, UART, or SSI for modes 1 and 2.
— Circular buffer mode (
CBM
)—specifies buffer wrapping for mode 1.
— Channel mode (
CMODE
)—selects memory-to-memory (mode 0), peripheral-to-memory (mode 1), or mem-
ory-to-peripheral (mode 2).
— Software DMA request enable (
SDRQ_E
)—enables software trigger used in modes 1 and 2.
— Software trigger DMA request (
SDRQ
)—software trigger used in modes 1 and 2.
— Channel transfer size (
CTS
)—selects 8-bit, 16-bit, or 32-bit transfers.
— Channel increment source address (
CIS
)—selects auto source address increment during burst read.
— Channel increment destination source address (
CID
)—selects auto destination address increment during
burst write.
— Channel start (
CS
)—begin the transfer.
Channel Priority:
The DMA controller has the highest priority for accessing the system bus. When bursts are transferred, the DMA
channel gets uninterrupted access to the system bus. If hold states are specified, the DMA channel deasserts its
bus request signal for one or more cycles following each write access to relinquish control of the system bus to the
ARM
.
DMA channels have a fixed priority, with channel 0 having the highest priority and channel 3 having the lowest pri-
ority.
Operational Comments:
To prepare for a DMA transfer, the required values are to be stored in the registers of one of the DMA channels, but
with the start bit (
CS
) of the
DMA control register
(see Table 36 on page 62)
set to 0. The transfer begins when
the start bit is set to 1. If the transfer completes, the start bit is automatically set to 0. In memory-to-memory mode
(mode 0), the core is stalled for the duration of the transfer burst. The maximum burst size is 256 words.
For a DMA transfer to or from a FIFO, writing 0 to the start bit prematurely terminates the transfer. When the DMA
channel is active, the
address
and
count registers
are read but not written.
The source and destination addresses satisfy alignment restrictions. If a word is being transferred, address bits 1:0
of the address are 0; if a half-word is transferred, address bit 0 is zero. Failure to follow alignment restrictions
causes the transfer to be terminated and an exception fault recorded in the
DMA status register
(see Table 43 on
page 66)
.
The DMA controller transfers up to 64 k-1 [bytes/half-words/words] at a time. Byte transfer to or from internal RAM
is available to support data transfer to or from peripheral modules. Mixed size transfers are not supported.