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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 213/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
211
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
15 Synchronous Serial Interface (SSI)
(continued)
flag is set, and an interrupt, if enabled, is generated. The
MDOSDI
line stays high before the transfer begins and
after it ends. This is useful in multiple master systems where the
MDOSDI
line is always at a known state whenever
the control of the bus is relinquished to another master.
15.3.2.2 Slave
On the slave side, the data is sampled from
MDOSDI
at the falling edge of
SCK
and shifted onto
MDISDO
at the
rising edge if
SPOL
= 0. If
SPOL
= 1, the sampling and shifting edges are reversed. The received data is buffered
at the end of seven and a half shift clock cycles (i.e., on the eighth sampling
SCK
edge), the
SDONE
flag is set, the
interrupt, if enabled, is generated, and the end of transfer is indicated. The output, however, remains valid until
SSN
is deasserted. At that time, the
MDISDO
pin stops driving.
15.3.3 Transfer Start
Every SSI transfer consists of an initiation period, followed by eight
SCK
cycles if the 8-bit data transfer takes
place, and finally the ending period. The details for the data transfer were considered in the previous section. Here
the initiation period is discussed for each of the different formats selected for the master and slave modes of oper-
ation.
If the SSI is configured as a master, all transfers are initiated by a write to the
SSI data register
. Such a write is
necessary even if the master is only interested in receiving data from the slave. There is a delay of three system
clock cycles after the write access before the start of the serial transfer. If
SPHA
= 0,
SCK
remains at its idle state
for the first half of the cycle following the write to the
SSI data register
. If
SPHA
= 1, the transfer cycle begins
immediately with the
SCK
going from its inactive level to the active level.
If the SSI is configured as a slave and
SPHA
= 0, a transfer begins if the
SSN
line is pulled low. The MSB of the
data written in the slave
SSI data register
initially appears on the
MDISDO
line. If the SSI is configured as a slave
and
SPHA
= 1, a transfer begins with the first active edge of
SCK
, provided that the slave is selected (
SSN
asserted).
15.3.4 Transfer End
A transfer is complete if all 8 bits are shifted in serially, the data is transferred to the read data buffer, and the
SDONE
flag is set. The interrupt signal (
IRQ
) will be active if
SDONEE
is set in the
SSI interrupt enable register
.
15.3.4.1 Master Operation
If the SSI is configured as a master, the received byte is transferred to the read-buffer at the end of eight
SCK
clock
cycles. The
SDONE
flag is set after a delay (independent of the
SCK
rate) of one system clock cycle.
15.3.4.2 Slave Operation
If the SSI is configured as a slave, the ending period depends on the value of
SPHA
. If
SPHA
= 0,
SDONE
is set at
the end of the eighth
SCK
cycle (one-half
SCK
cycle after the last bit is sampled by the slave). If
SPHA
= 1,
SDONE
is set in the middle of the eighth
SCK
cycle (at the time the last bit is sampled). Since the master always
ends the transfer at the end of the eighth
SCK
cycle, the
SDONE
bit in the slave completes the transfer
if
SPHA
= 1.
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