
Agere Systems Inc.
115
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
10 Ethernet 10/100 MAC
(continued)
10.7.16 MAC PHY Powerdown Register
Table 93. MAC PHY Powerdown Register
10.7.17 MAC Controller Transmit Control Register
Table 94. MAC Controller Transmit Control Register
Address 0xE001 0200
Bit #
Name
Bit #
31:2
31:2
RSVD
1
0
PHY1
PHY0
Name
RSVD
PHY1
Description
Reserved.
PHY1. Read/write. If
1, power down.
Default = 1.
PHY0. Read/write.
1
0
PHY0
Default = 0.
Address 0xE001 0800
4
TLME
CNTLXMIT
Bit #
Name
Bit #
15
14
5
4
15
14
5
3
2
1
0
RXMT
RRND
TRME
TXABORT
Description
RESTARTFIFO
RSTFIFO
Name
RXMT
RRND
TRME
TLME
Reset transmit.
Must be written to 0 before attempting to use transmitter.
Reset random counter (write 1, then write 0).
Transmitter enable.
Set to 1 to enable transmission of packets.
Transmitter late mode enable.
When set to 1, an internal late counter counts the
number of transmit clocks from transmit start until the packet is sent or transmission
is halted. If the late counter matches the late alarm value (
ALARMVALUE
;
see Table
79 on page 108
) an interrupt will be generated if enabled. This allows the processor
to know when real time packets are no longer meaningful due to excessive transmis-
sion delay.
Control transmit request.
When this bit is set, the MAC control frame programmed in
register addresses 0xE001 0014 to 0XE001 002C will be transmitted.
3
CNTLXMIT
This bit is self-clearing.
Transmit abort (active-high).
Used to stop a transmission ungracefully. The transmit-
ter immediately terminates a transmission if this input is set.
TXABRT
should be held
high for two or more
TX_CLK
cycles. When a packet is aborted during preamble, the
preamble is completed and the
APNDCRC
and
INVCRC
inputs are followed. If
TXABORT
is activated during transmission, transmission immediately stops, and the
APNDCRC
and
INVCRC
inputs are followed.
2
TXABORT
This bit is held high for two
TX_CLK
cycles, then self-clears.
Restart FIFO. This bit only resets the read pointer of the transmit FIFO.
Reset FIFO. This bit resets both the read and write pointers of the
transmit FIFO
.
1
0
RESTARTFIFO
RSTFIFO