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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 187/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
185
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
13 USB Host Controller
(continued)
Table 166. Hc Rh Port Status Register [1:NDP]
(continued)
Bit #
Field
Root Hub
Reset
0b
Read/Write
HCD
R/W
Description
HC
R/W
3
POCI
Port overcurrent indicator, (read).
This bit is only valid when the
root hub is configured in such a way that overcurrent conditions
are reported on a per-port basis. If per-port overcurrent reporting
is not supported, this bit is set to 0. If cleared, all power operations
are normal for this port. If set, an overcurrent condition exists on
this port. This bit always reflects the overcurrent input signal.
0 = no overcurrent condition.
1 = overcurrent condition detected.
Clear suspend status, (write).
The HCD writes a 1 to initiate a
resume. A resume is initiated only if this bit is set.
Writing a 0 has no effect.
Port suspend status, (read).
This bit indicates the port is sus-
pended or in the resume sequence. It is set by a write and cleared
when it is set at the end of the resume interval. This bit cannot be
set if it is cleared. This bit is also cleared when is set at the end of
the port reset or when the HC is placed in the USB resume state.
If an upstream resume is in progress, it should propagate to the
HC.
2
PSS
0b
R/W
R/W
0 = port is not suspended.
1 = port is suspended.
Set port suspend, (Write).
The HCD sets the bit by writing a 1 to
this bit. If
CCS
is cleared, this write does not set
PSS
; instead, it
sets
CSC
. This informs the driver that it attempted to suspend a
disconnected port.
Writing a 0 has no effect.
Port enable status, (read).
This bit indicates whether the port is
enabled or disabled. The root hub may clear this bit when an over-
current condition, disconnect event, switched-off power, or opera-
tional bus error such as babble is detected. This change also
causes
PESC
to be set. HCD sets this bit by writing set port
enable and clears it by writing clear port enable.
1
PES
0b
R/W
R/W
This bit cannot be set when
CCS
is cleared. This bit is also set, if
not already, at the completion of a port reset when reset status
change is set or port suspended when suspend status change is
set.
0 = port is disabled.
1 = port is enabled.
Set port enable, (write).
The HCD sets
PES
by writing a 1. If
CCS
is cleared, this write does not set
PES
, but instead sets
CSC
. This
informs the driver that it attempted to enable a disconnected port.
Writing a 0 has no effect.
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