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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話(huà)高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 166/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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164
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
13 USB Host Controller
(continued)
13.3.2 Hc Control Register
The
Hc Control register
defines the operating modes for the host controller. Most of the fields in this register are
modified only by the host controller driver, except host controller functional state and
remote wake-up connected.
Table 146. Hc Control Register
Address 0xE000 7004
7
HCFS
Bit #
Name
Bit #
31:11
RSVD
Key
10
9
8
IR
6
5
4
3
IE
2
1:0
RWE
Reset
RWC
BLE
CLE
PLE
CBSR
R/W
Description
HCD
—
R/W
HC
—
R
31:11
10
RSVD
RWE
—
0b
Reserved.
Remote wake-up enable. This bit is used by HCD to enable or
disable the remote wake-up feature upon the detection of
upstream resume signaling. When this bit is set and the
RD
bit in
Hc interrupt status register
(see Table 148 on page 167)
is set,
a remote wake-up is signaled to the host system. Setting this bit
has no impact on the generation of hardware interrupt.
Remote wake-up connected.
This bit indicates whether HC sup-
ports remote wake-up signaling. If remote wake-up is supported
and used by the system, it is the responsibility of system firm-
ware to set this bit during post. HC clears the bit upon a hard-
ware reset but does not alter it upon a software reset. Remote
wake-up signaling of the host system is host-bus-specific, and is
not described in this specification.
Interrupt routing. This bit determines the routing of interrupts
generated by events registered in
Hc interrupt status register
.
If clear, all interrupts are routed to the normal host bus interrupt
mechanism. If set, interrupts are routed to the system manage-
ment interrupt. HCD clears this bit upon a hardware reset, but it
does not alter this bit upon a software reset. HCD uses this bit as
a tag to indicate the ownership of HC.
Host controller functional state for USB.
9
RWC
0b
R/W
R/W
8
IR
0b
R/W
R
7:6
HCFS
00b
R/W
R/W
00: USB reset
01: USB resume
10: USB operational
11: USB suspend
A transition to USB operational
from another state causes SOF
generation to begin 1 ms later. HCD may determine whether HC
has begun sending SOFs by reading the start of frame field of
the
Hc interrupt status register
. This field may be changed by
HC only when in the USB suspend state. HC may move from the
USB suspend state to the USB resume state after detecting the
resume signaling from a downstream port. HC enters USB sus-
pend after a software reset, whereas it enters USB reset after a
hardware reset. The latter also resets the root hub and asserts
subsequent reset signaling to downstream ports.
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