194
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
14 IrDA_ACC and UART_ACC
(continued)
14.2.8 Tx/Rx FIFO Register
The
Tx/Rx FIFO register
provides access to the transmitter and receiver FIFOs. A write to this register writes a
character to the transmitter FIFO. A read from this register reads a character from the receiver FIFO. Both FIFOs
are reset upon all system resets.
The ACC loads the
output shift register
(see Figure 22 on page 187)
with data from the FIFO prior to transmitting
that character and stores the received character in the FIFO after it has been completely received, including its
stop character.
A read from an empty Rx FIFO returns the byte from the FIFO position just after the last Rx FIFO read, but it does
not change the status of the Rx FIFO.
Table 177. Tx/Rx FIFO Register
14.2.9 IrDA Feature Register
The
IrDA feature register
is used to control the IrDA and the device MUX. The
IrDA feature register
is set to all
zeros on any reset.
Table 178. IrDA Feature Register
Address—IrDA 0xE000 801C, UART 0xE000 901C
31:10
RSVD
EXFI
Bit #
Name
Bit #
31:10
9
9
8
7:0
CHA
DB9
Name
RSVD
EXFI
Description
Reserved.
Extended FIFO character mode.
In 9-bit data mode, the value of bit 9 in the transmit FIFO
selects between the normal character mode (i.e., 1 start, 9 data bits, 1 optional parity, 1 stop),
and the break/idle mode (i.e., synchronous transmission of a break or idle line conditions for
11 baud intervals). In 8-bit data mode, this bit is ignored on writes and always read as zeros.
If 1, the character is an extended character.
If 0, the character is a normal character.
Data bit 9 mode.
Bit 8 is the ninth data bit in 9-bit data mode. In 8-bit data mode, it is ignored
on writes and always reads as zeros.
Character.
Character to transmit if written to. Character received if read from.
8
DB9
7:0
CHA
Address 0xE000 8020
9
SEL
Bit #
Name
Bit #
31:10
9
8
31:10
RSVD
8
7:0
PWC
IDE
Name
RSVD Reserved.
SEL
Select. Must be 0.
IDE
IrDA enable. Enables the IrDA.
Description
If 1, the IrDA is active and the IrDATx and IrDARx pins are driven by the IrDA feature.
If 0, the IrDA is disabled and the IrDATx and IrDARx pins are driven without the IrDA I/O formatter.
Pulse width count. Pulse width count value.
7:0
PWC