
170
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
13 USB Host Controller
(continued)
13.3.6 Hc Interrupt Disable Register
Each disable bit in the
Hc interrupt disable register
corresponds to an associated interrupt bit in the
Hc interrupt status register
. The
Hc interrupt disable register
is coupled with the
Hc Interrupt enable register
.
Thus, writing a 1 to a bit in this register clears the corresponding bit in the
Hc interrupt enable
register
, whereas
writing a 0 to a bit in this register leaves the corresponding bit in the
Hc interrupt enable
register
unchanged. On
read, the current value of the
Hc interrupt enable
register
is returned.
Table 150
.
Hc Interrupt Disable
Register
Address 0xE000 7014
6
5
RHSC
FNO
Bit #
Name
Bit #
31
MIE
Key
30
OC
29:7
RSVD
Read/Write
HCD
R/W
4
3
2
1
0
UE
RD
SF
WDH
SO
Reset
Description
HC
R
31
MIE
0b
Master interrupt enable.
A 0 written to this field is ignored by HC.
A 1 written to this field disables interrupt generation due to events
specified in the other bits of this register. This field is set after a
hardware or software reset.
Ownership change.
30
OC
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to ownership change.
Reserved.
Root hub status change.
29:7
6
RSVD
RHSC
—
0b
—
R/W
—
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to root hub status change.
Frame number overflow.
5
FNO
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to frame number overflow.
Unrecoverable error.
4
UE
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to unrecoverable error.
Resume detect.
3
RD
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to resume detect.
Start of frame.
2
SF
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to start of frame.
Writeback done head.
1
WDH
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to HcDoneHead writeback.
Scheduling overrun.
0
SO
0b
R/W
R
If 0 = Ignore.
If 1 = Disable interrupt generation due to scheduling overrun.