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參數(shù)資料
| 型號： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級RISC機（ARM）的以太網(wǎng)使用IEEE 802.1q的服務質量 |
| 文件頁數(shù)： | 214/248頁 |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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212
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
15 Synchronous Serial Interface (SSI)
(continued)
15.3.5 Interrupt Generation
If the SSI interrupt is enabled in the interrupt controller’s
SSI interrupt
enable register
, the SSI asserts its interrupt
request whenever a byte is successfully shifted in and copied to the read data buffer (i.e., if the
SDONE
bit is true,
or if a mode fault or read overrun occurs).
The interrupt is cleared if
SDONE
,
MODF
, and
RD_ORUN
are cleared.
15.3.6 Status Flags and Error Conditions
The
SSI interrupt register
contains four read-only status bits,
SDONE, WCOLL, MODF
, and
RD_ORUN
.
There is another error condition that occurs if the SSI is configured as a slave and a transfer is aborted by the mas-
ter unit pulling
SSN
high or the slave software writing
SSI control register 1
bit 10:0 before the transfer is com-
plete. This error condition is not indicated by the status flags and is detected by a software protocol.
The status and error conditions are described below.
15.3.6.1 SDONE
SDONE
is a status flag that indicates the end of a transfer. At the end of a transfer, the
SDONE
bit of
SSI interrupt
register
is set. If the
FASTCLEAR
bit of
SSI control register 2
= 1, the
SDONE
flag is cleared by a read or write
of the
SSI data register
. If
FASTCLEAR
of
SSI control register 2
= 0, the
SDONE
flag is cleared by writing to the
SDONE
bit in the
SSI interrupt register
to clear the SSI interrupt.
15.3.6.2 WCOLL Flag
The
WCOLL
bit of
SSI interrupt register
indicates that a write collision error occurred. A write collision error is
detected if a write to the
SSI data register
is attempted while a transfer is in progress. The transfer continues but
the data that caused the error may or may not be written to the transmit buffer. Because of this uncertainty, a trans-
fer that experiences a write collision error is aborted and should be tried later. If the SSI is configured as a master,
a transfer begins when data is written to the
SSI data register
and ends when the received data is transferred to
the read data buffer, at which time
SDONE
is set.
Note:
A write collision error should not occur in master mode if the driver software is structured correctly.
If the SSI is configured as a slave, it has no way to predict when the master will initiate a transfer. However, if
SPHA
= 0, the true end of the transfer does not occur until the
SSN
signal is deasserted. In this case, the user
determines both the beginning and the end of transfer by polling the
SSN
line using bit 0 of
SSI control register 2
.
The
SPHA
= 1 mode is more problematic since
SSN
is held low constantly or between transfers so
SSN
cannot
always be used to tell whether a transfer is in progress. The end of transfer is determined via the
SDONE
flag in the
SSI interrupt register
, but there is no satisfactory way of determining the beginning of transfer. Therefore, write
collisions are possible for this mode. However, these write collisions in the slave are avoided by writing
SSNEN
of
SSI control register 1
to zero before writing the slave’s
SSI data register
. If
SSNEN
of
SSI control register
1 is
written to 0 during a transfer, the transfer terminates.
The
WCOLL
flag, once set, is cleared by writing a 1 to the
WCOLL
field in the
SSI interrupt register
, followed by
a read or write of the
SSI data register
.
15.3.6.3 MODF
The
MODF
bit indicates a mode fault. A mode fault error occurs when the SSI is configured as a master and the
SSN
line is asserted. The
SSNEN
bit of
SSI control register 1
(see Table 183 on page 204)
is enabled for the
SSN
line to be recognized in master mode. If a mode fault is detected, the master SSI immediately disables its
SCK
clock and
MDOSDI
data output pins in order to eliminate any bus contention.
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