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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 197/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
195
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
14 IrDA_ACC and UART_ACC
(continued)
Table 179. ACC Interrupt Register
Address 0xE000 8040, 0xE000 9040
10
TXSREI
3
RXFEI
Bit #
Name
Bit #
Name
Bit #
31:12
11
31:12
RSVD
5
RXNII
Name
RSVD
TXNDI
11
9
8
7
6
TXNDI
4
RXPEI
TXFHI
2
RXOEI
Description
TXFEI
1
RXFHI
RSVD
0
RXFFI
RXFNEI
—
—
Reserved.
Transmitter no data interrupt. This bit is a 1 when the
transmitter shift register
is empty and
the transmitter FIFO is empty and the
TXON
bit is set to 1. If the
TXNDIE
is set when this bit is
1, an interrupt will be generated.
This bit is read-only.
TXSREI Transmitter shift register empty interrupt.
This bit is set when the
transmitter shift register
becomes empty. If the interrupt is enabled in the
interrupt
enable register
and the
TXON
bit is
set to 1, an interrupt will be generated. A new byte of data must be loaded into the
transmit
shift register
to re-enable this bit to transition to 1 again.
TXFHI
Transmitter FIFO half-empty interrupt. This bit is a 1 when the transmit FIFO is less than half
full. The FIFO condition, that causes the interrupt to occur must be removed, (i.e., by writing the
FIFO) to remove this bit. This bit is read-only. This interrupt must be disabled if the processor
does not have any more data to place in the transmitter to prevent an interrupt from always
being asserted.
This bit is masked and will be a 0 if the
TXON
bit is not set to a 1.
TXFEI
Transmitter FIFO empty interrupt. This bit is a 1 when the transmit FIFO is empty. The FIFO
condition that caused the interrupt must be removed (i.e., by writing the FIFO) to remove this
bit. This bit is read-only. This interrupt must be disabled if the processor does not have any
more data to place in the transmitter to prevent an interrupt from always being asserted.
This bit is masked and will be a 0 if the
TXON
bit is not set to a 1.
RSVD
Reserved.
RXFNEI Receiver FIFO not empty interrupt. This bit is a 1 when the receive FIFO is not empty. The FIFO
condition that caused the interrupt must be removed (i.e., by reading the FIFO) to remove
this bit.
This bit is read-only.
RXNII
Receiver not idle interrupt. This interrupt is set when the receiver becomes not idle. If the
receiver not idle interrupt is enabled while this bit is 1, an interrupt to the processor will be gen-
erated. This bit is cleared by writing a 1 to this bit location. If the receiver is still not idle when
this bit is cleared, it must go idle and then not idle again for a new interrupt to be generated.
Note: RXNII
does not indicate that an entire character has been received. It indicates that a
character receipt is in progress. To verify that an entire character has been received, poll
the
RFE
bit in the
FIFO status register
(see Table 172 on page 191)
.
RXPEI
Receive data parity error. This bit is set when a parity error is detected in the received data. If
the parity error interrupt enable bit is set while this bit is 1, an interrupt will be generated.
This bit is cleared by writing a 1 to this bit location.
RXFEI
Receive data framing error. This bit is set when a framing error is detected in the received data.
If the framing error enable bit is set while this bit is 1, an interrupt will be generated.
This bit is cleared by writing a 1 to this bit location.
10
9
8
7
6
5
4
3
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