- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371179 > T8302 T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q PDF資料下載
參數(shù)資料
| 型號： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級RISC機（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁數(shù)： | 34/248頁 |
| 文件大小： | 7321K |
| 代理商： | T8302 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁
32
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
4 Reset/Clock Management
(continued)
The four conditions are mutually exclusive, and appropriate actions can be taken within the boot code depending
on which bit is set.
When one of these reset sources becomes active, the appropriate reset source is recorded in the
reset status
(control/clear) register
(see Table 13 on page 40)
. A reset signal is sent to the
ARM
940T core and all of the
peripheral blocks are reset. The internal resets are deasserted synchronously with the falling edge of the system
clock after the source of the reset is deasserted. The
RTS0N
pin is maintained active-low until released by software
via the
reset peripheral control (read, clear, set) register
(see Table 14 on page 41)
.
A reset from any of the four sources previously mentioned immediately causes the following:
I
The clock source is switched to the 11.52 MHz external input with the clock divider set to 1.
I
The PLL is powered up and its programmable registers are preset.
I
The EMI (external memory interface) and the peripheral devices are powered up in their default power-on state.
(In general, most register bits in the reset/clock management controller are set to a default on state, whereas
most peripheral registers are reset to 0. Any exceptions to this will be specifically noted when the register bits are
discussed.)
I
The internal reset signal
(INT_RST)
, as well as the external reset (
RTS0N)
signal, is asserted immediately when-
ever any of the four reset sources are asserted. The external
RTS0N
signal remains active until cleared in the
reset peripheral control register
(read, clear, set)
;
see Table 14 on page 41
.
Deasserting
RTS0N
is accom-
plished by writing 0 to the
ERS
bit in the
reset peripheral control clear register
.
4.1.2 Operation of the Clock Switching Logic
The clock switching logic is controlled by software. For example, when switching from the external clock to the PLL
clock, the
PLLE
enable bit in the
clock control register
(see Table 10 on page 38)
is set to 1 to enable the PLL,
then the
PLLC
bit in the
clock management register
(see Table 7 on page 37)
is set to 1. The PLL can be shut
down to conserve power by resetting the enable bit (
PLLE
).
4.1.2.1 PLL Operation
The PLL oscillator is controlled by
PLLE
of the
clock control register
(see Table 10 on page 38)
. The PLL gener-
ates a clock signal when
PLLE
is set to 1. It typically takes about 30 μs for the PLL oscillator to restart and lock in
from the inactive state (with a maximum of 250 μs).
The input to the PLL comes from the input clock
EXT_CLK
. The PLL cannot operate without this external input
clock.
To use the PLL clock, first stabilize the clock output and then lock it to the programmed frequency. The clock switch-
ing logic waits until lock occurs before switching to the PLL clock.
The frequency of the PLL output clock (
PLL_CLK
) is determined by the values loaded into the 3-bit N divider and
the 5-bit M divider
(see Table 12 on page 39)
. When the PLL clock is selected and locked (by setting
PLLC
in the
clock management register
) the frequency of
PLL_CLK
is related to the frequency of
EXT_CLK
by the following
equation:
PLL_CLK = EXT_CLK x (MBITS + 1)/(NBITS + 1)
The coding of the
Mbits
and
Nbits
is described
in Table 12 on page 39
.
For example:
The frequency of
PLL_CLK
is designed to be 288 MHz in this application.
288 MHz = 11.52 MHz x (24 + 1)/(0 + 1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T8502 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8503 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8531A | T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8531 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8532 | T8502 and T8503 Dual PCM Codecs with Filters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302B | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302F | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303ABNAD | 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。