
Agere Systems Inc.
133
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.5 Repeater Slice Register Map
Table 113. Repeater Slice Register Map
Signal
MIIRX_DV
Type
O
Description
MII receive data valid.
In 10 Mbits/s mode,
MIIRX_DV
indicates that
MIIRXD [3:0]
contains decoded nibbles of
data from the MAC.
MIIRX_DV
will transition synchronously with respect to the
MIICLK
.
MIIRX_DV
will remain asserted continuously from the first nibble of the frame through
the last nibble and will be gated to the first
MIICLK
that follows the final nibble.
MIIRX_DV
is not looped back on a transmit from the MAC. It is only asserted due to
either repeater slice ports being active or the expansion port being the source of data.
In 100 Mbits/s mode,
MIIRX_DV
indicates that
MIIRXD [3:0]
contains decoded nibbles
of data from the backplane segment.
MIIRX_DV
will transition synchronously with
respect to the
MIICLK
.
MIIRX_DV
will remain asserted continuously from the first nibble
of the frame through the last nibble and will be negated prior to the first
MIICLK
that fol-
lows the final nibble.
MIIRX_DV
will encompass the frame, starting no later than the
start of frame delimiter and excluding any end-of-frame delimiter.
MIIRX_DV
is not
looped back on a transmit from the MAC.
MII receive error.
MIIRX_ER
O
In 10 Mbits/s mode,
MIIRX_ER
is driven low.
In 100 Mbits/s mode,
MIIRX_ER
indicates the backplane segment has sensed an error
code in the current frame.
MIIRX_ER
will transition synchronously to
MIICLK
and
remain asserted for the duration of the error being sensed.
MII carrier sense or MAC serial 10 Mbits/s carrier sense.
MIICRS
will be asserted by
the backplane segment when the segment is nonidle.
MIICRS
will be deselected when
the segment has gone idle. The backplane segment will ensure that
MIICRS
remains
asserted throughout the duration of a collision condition. The backplane segment will
loopback
MIITX_EN
as
MIICRS
when the MAC is transmitting to the backplane seg-
ment.
MII collision or serial 10 Mbits/s MAC collision.
In 100 Mbits/s and 10 Mbits/s modes,
MIICOL
will be asserted by the backplane seg-
ment to signal a collision on the medium and will remain asserted while the collision
condition exists.
MIICOL
is clocked out with
MIICLK
.
MIICRS
O
MIICOL
O
Register
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/O
R/W
R/W
Address
Reserved.
Global maximum frame size register
(see Table 114 on page 134)
.
Global configuration register
(see Table 115 on page 135)
.
Port control register for port 0/1
(see Table 116 on page 136)
.
Port configuration register 0, for port 0/1
(see Table 117 on page 136)
.
Port configuration register 1, for port 0/1
(see Table 118 on page 138)
.
Global port status register, for port 0/1
(see Table 121 on page 141)
.
Global interrupt enable register
(see Table 119 on page 139)
.
Global interrupt status register
(see Table 120 on page 140)
.
0xE001 2000:2004
0xE001 2008
0xE001 200C
0xE001 2020/2220
0xE001 2024/2224
0xE001 2028/2228
0xE001 2030/2230
0xE001 2180
0xE001 2188
Table 112. Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B
(continued)