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參數(shù)資料
| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 126/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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124
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.1 MII Transmit and Receive Interface
The transmit and receive interface has three major sections: the repeater slice, the PHY interface, and the back-
plane interface.
11.1.1 Repeater Slice Interface
There is a 2-channel repeater slice: slice 0 and slice 1. Slice 0 is connected to the master PHY going to the net-
work. The master clocks are generated from PHY 0. Slice 1 is connected to the slave PHY going to the personal
computer. The repeater provides a centralized hub that retransmits incoming data simultaneously upon reception
while retiming and strengthening the signal. Management software or hardware will need to ensure that the ports
that feed a segment have the same speed.
The repeater core, that includes the repeater state machine, the partition state machine, and the event generator,
controls data flow in both directions.
I
The repeater state machine enables the device to operate properly according to the
IEEE
Standard 802.3u 1995
including collision detection and fragment extension.
I
The partition state machine monitors the receive data stream for excessive and long collisions and disables
receipt from the port if collision count or length thresholds are exceeded. Partitioning can be disabled by setting
DAP
of the
port configuration register 0
to 1
(see Table 117 on page 136)
.
11.1.2 PHY Interface
In 100 Mbits/s mode, the PHY interface conforms to the
IEEE
802.3 media-independent interface definition. On the
receive side,
RXDx
is clocked onto the repeater slice using the recovered clock from the PHY,
RX_CLK
, when
RX_DVx
is asserted. It also accepts and forwards
RX_ERx
as part of the data stream to the backplane. On the
transmit side,
TXDx, TX_DVx
, and
TX_ERx
are clocked out using the 25 MHz
TX_CLK
clock.
Alternatively, an internal 25 MHz clock can be used to transfer data and control to the PHY via a register bit in the
global configuration register
(see Table 115 on page 135)
. The
COL
signal from the PHY
(see Table 110 on
page 129)
is monitored for collisions on the link, and the
CRS
signal is monitored for the presence of a received
carrier.
In 10 Mbits/s mode, data is transferred to and from the PHY using a 7-pin serial data interface. Data and envelope
information are received from the PHY on
RXD[0]
and
CRS
in combination with
RX_CLK
, respectively. Data and
envelope information are transmitted to the PHY on
TXD[0
] and
TX_EN
with
TX_CLK
, respectively.
The 10 Mbits/s mode will always use the
TX_CLK
input to transfer data to the PHY. The
COL
pin is monitored by
the repeater slice for collision presence.
The repeater slice interfaces to 10 Mbits/s PHYs with a 7-pin serial interface, and to 100 Mbits/s PHYs with the
standard MII interface. As previously mentioned, there is an option in 100 Mbits/s mode to use an internal
25 MHz clock to transfer data and control to the PHY. This is controlled via
TXCPIN
in the
global configuration
register
(see Table 115 on page 135)
.
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