
70
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
7 Programmable Timers
The programmable timers module supports two timer functions: interval timer (IT) and watchdog timer (WT). Fea-
tures of the timer module are as follows:
I
Watchdog alarm interrupt
I
Watchdog alarm reset
I
Four interval timers
I
Generation of a shared interrupt request from the four interval timer channels
7.1 Timers Operation
All of the counters in the programmable timer module operate synchronously with the system clock. The count
rates are controlled by a clock prescaler that generates count enable signals at intervals of 2
n
of the system clock
rate. The interval timer and the watchdog timer functions independently select a count rate.
Figure 8 shows the programmable timer architecture.
5-8227(F)
Figure 8. Programmable Timer Architecture Block Diagram
7.2 Interval Timer (IT)
The interval timer function supports four independent timers running off a common prescaler. Each timer consists
of a 16-bit, free-running counter, which increments at the selected count rate, and an
IT maximum count register
(see Table 53 on page 77)
that determines the interval.
The following text describes the general usage of the interval timers:
I
Set the
count rate register
(see Table 47 on page 74)
to divide the system clock for the interval timers. The
count rate is selected by programming the interval timer count rate field (
ITR
) with an index between 0 and 11.
I
Set the
IT maximum count register
(see Table 53 on page 77)
to set the timer interval. The
IT
count register
(see Table 53 on page 77)
is loaded with the
IT maximum count register
value.
I
Enable timer by setting the
ITEx
bit in the
timer control register
(see Table 52 on page 76)
. When the timer is
enabled, the
IT count rate register
begins decrementing.
P
WATCHDOG
TIMER
FUNCTION
INTERVAL
TIMER
FUNCTION
CONTROL/
STATUS/
MASK
INTERRUPT REQUEST
32 kHz CLOCK
PERIPHERAL CLOCK
WIC
PERIPHERAL CLOCK
WATCHDOG TIMER RESET