136
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.5.3 Port Control Registers, for Port 0, 1
Table 116. Port Control Registers for Port 0, 1
11.5.4 Port Configuration Register 0 for Port 0, 1
This register is used to configure the repeater port as described below. This register will default to the values in
parenthesis after reset.
Table 117. Port Configuration Register 0 for Port 0, 1
Address—Port 0 (0xE001 2020), Port 1 (0xE001 2220)
31:1
RSVD
State on RST
(0)
Reserved.
(0)
Software reset. When this bit is set to 1, the port repeater digital cir-
cuits are reset to the power-on state.
Bit #
Name
Bit #
31:1
0
SRST
Name
RSVD
SRST
Description
0
Note:
This bit is provided primarily for diagnostic and debugging pur-
poses and is
not
intended to be used in place of the
RESET
pin at system start-up. A full hardware reset is required to
place the entire chip in a known state. All registers will retain
their values.
Write
1
to reset.
Write 0 to get out of reset.
Addresses—Port 0 (0xE001 2024), Port 1 (0xE001 2224)
14:12
11:10
CRSDELAY[2:0]
RSVD
State on RST
(0)
Reserved.
CRSDELAY[2]
CRSDELAY[1]
CRSDELAY[0]
(0)
10 Mbits/s mode.
Bit #
Name
Bit #
31:15
14:12
31:15
RSVD
Name
RSVD
9
8
7
6
5:0
RXDVAV
XMTE
Description
RCVE
DAP
RSVD
(1)
(0)
CRS delay.
In 10 Mbits/s mode,
CRS
is never delayed, so these bits are ignored in
In 100 Mbits/s mode, these bits are used to set a delay for the start of
preamble regeneration from the receipt of
CRS
from the PHY. This regis-
ter is typically programmed to a value other than the default (100) when
the repeater is connected to a T4 PHY. Due to the variability of T4 receiv-
ers and the requirement for accurate preamble generation on the trans-
mit side, this value sets up a count to adjust the start of preamble. The
contents of this register will be a 3-bit binary value that represents the
number of additional
MSTCLK
cycles to wait after the assertion of
CRS
to begin preamble generation on the backplane (i.e., 000 = 0
MSTCLK
s,
111 = 7
MSTCLK
s).