
42
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
4 Reset/Clock Management
(continued)
Table 15. RTC External Divider Register
4.2.12 RTC Clock Prescale Registers
The
RTC
clock prescale registers
indicate the value by which to divide the input clock to get the current clock. If
all zeros, the input clock is passed on without division. Only one of the divisor bits in the
RTC
clock prescale reg-
isters
may be set at one time. If more than one bit is set, the lowest order bit set will determine the divisor.
The format for each of the
RTC clock prescale registers
is identical and is as follows:
Table 16. RTC Clock Prescale Registers
Address 0xE000 0050
Bit #
Name
Bit #
31:16
15:0
31:16
RSVD
15:0
ECD
Name
RSVD
ECD
Description
Reserved.
RTC divider register. The clock changes state from high to low or low to high every time the
RTC divider register
counts down to 0. It is then reloaded with the
ECD
value entered by the
user.
Prescaler
EXT_PRESCALER
PLL_PRESCALER
USB_PRESCALER
Address
0xE000 0054
0xE000 0058
0xE000 005C
Prescaler Input
EXT_CLK
PLL_CLK
USB_CLK
Prescaler Output
PRESCALE_EXT_CLK
PRESCALE_PLL_CLK
PRESCALE_USB_CLK
Addresses 0xE000 0054:0xE000 005C
5
D8
Bit #
Name
Bit #
31: 7
6
31:7
RSVD
6
4
3
2
1
0
D16
D6
Description
D5
D4
D3
D2
Name
RSVD Reserved.
D16
Indicates that the prescaler input is divided by 16.
If 1, divide the clock by 16.
If 0, do not divide the clock by 16.
Indicates that the prescaler input is divided by 8.
5
D8
If 1, divide the clock by 8.
If 0, do not divide the clock by 8.
Indicates that the prescaler input is divided by 6.
4
D6
If 1, divide the clock by 6.
If 0, do not divide the clock by 6.
Indicates that the prescaler input is divided by 5.
3
D5
If 1, divide the clock by 5.
If 0, do not divide the clock by 5.
Indicates that the prescaler input is divided by 4.
2
D4
If 1, divide the clock by 4.
If 0, do not divide the clock by 4.