
Agere Systems Inc.
85
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
8 External Memory Interface (EMI)
(continued)
Table 58.
Chip Select Configuration Register FLASH_CS
(continued)
8.5.2 Chip Select Configuration Registers CS1, CS2, CS3
Table 59. Chip Select Configuration Registers CS1, CS2, CS3
Bit #
10
Name
HD
Description
Hold disable. Disables the hold states between accesses in a multicycle read transaction.
If 1, hold states are suppressed between the access.
If 0, each access is followed by the specified number of hold states.
Note:
The hold states at the end of the transaction are not suppressed by this bit.
Reset value = 0.
Reserved.
Enable or disable
EXWAIT
pin.
9
8
RSVD
WT
If 1,
EXWAIT
is enabled.
If 0,
EXWAIT
is disabled.
Reset value = 0.
Setup cycle. Adds an extra cycle of setup time to the address and control signals with
respect to the chip select.
7
SET
If 1, the extra setup cycle is added.
If 0, the extra setup cycles is not added.
Reset value = 0.
Reserved.
Hold states. The number of hold states inserted after each read or write access
(see Table
60 on page 87)
.
6
RSVD
HS
5:4
Reset value = 00.
Wait-states.
The number of wait-states inserted during each read or write access
(see Table
61 on page 87)
.
3:0
WS
Reset value = 1111.
Addresses—CS1 (0xE000 3004), CS2 (0xE000 3008), CS3 (0xE000 300C)
31:14
13
12
11
10
RSVD
UBE
ENA
RSVD
HD
Name
RSVD
Reserved.
UBE
Use byte enables. Used for devices which are 16-bit devices and use byte enables. Byte
writes to these devices are illegal if this bit is not set.
Bit #
Name
Bit #
31:14
9
8
7
6
5:4
HS
3:0
WS
RSVD
Description
WT
SET
BS
13
If 1, byte enables are used by the device.
If 0, no byte enables are used by the device.
Enable chip select.
12
ENA
If 1, the chip select is enabled.
If 0, the chip select is disabled.
Reset value = 0.