參數(shù)資料
型號(hào): T8302
英文描述: T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q
中文描述: T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)(ARM)的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量
文件頁(yè)數(shù): 127/248頁(yè)
文件大小: 7321K
代理商: T8302
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Agere Systems Inc.
125
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
Port configuration register
bit
CRSDELAY
(see Table 117 on page 136)
, sets a delay for the start of preamble
regeneration from the receipt of
CRS
from the PHY.
CRSDELAY
should be set to its default value of 0x4, except for
T4 applications.
Due to the variability of T4 receivers and the requirement for accurate preamble regeneration on the transmit side,
the
CRSDELAY
value sets up a count between 0 and 7 for use in tweaking the start of preamble.
Depending on the phase relationship between
MAINCLK
and
RX_CLK
, simulation may show the repeater working
with a value of one less than this calculated value. This is the worst case and therefore is a proper calculation.
The
following formula should be used to calculate the proper value for
CRSDELAY
:
CRSDELAY
value = [(Maximum number of preamble nibbles received from PHY) – 11] + (
CRS
to
RX_DV
delay/40 ns rounded up)
Example 1: All 14 possible preamble nibbles are received from the PHY. The maximum delay from
CRS
active to
RX_DV
active is 41 ns.
CRSDELAY
value = (14 – 11) + 1 = 4
Example 2: A maximum of 10 of the 14 possible preamble nibbles are received from the PHY. The maximum
delay from
CRS
active to
RX_DV
active is 40 ns.
CRSDELAY
value = (10 – 11) + 1 = 0
If the above calculation results in a negative number, use zero for
CRSDELAY
. If all 14 preamble nibbles are
received from the PHY, the maximum
CRS
active to
RX_DV
active allowable delay is 160 ns.
11.1.3 Backplane Interface
The architecture of the repeater slice requires the use of external interconnection circuitry (backplane) that must
include at least a switch matrix to form a complete repeater unit. The receive path of each port of the chip is in no
way coupled to the transmit path of any port as far as the data path is concerned. It is assumed that the repeater
slice will interface to an external device, which in turn will be responsible for creating the collision domains to which
the repeater slice repeater ports attach. The backplane segment provides this switch function.
The backplane segment contains one 10 Mbits/s internal segment and one 100 Mbits/s segment. Each repeater
slice port feeds the 10 Mbits/s or the 100 Mbits/s data to the backplane segment. Optionally, the backplane seg-
ment 10 Mbits/s can be converted to a 100 Mbits/s segment, so that two 100 Mbits/s segments exist. When the
10/100 Mbits/s segment is configured for 100 Mbits/s operation, there can be no 10 Mbits/s segment connections
since only two segments exist.
Regardless of which operating mode is selected, it is assumed that data will be looped back to all ports on the
same segment, including the port that is sourcing the data. It also provides a nibble mode MAC interface for both
10 Mbits/s and 100 Mbits/s operations. The assignment of the port to a segment depends on the per-port
SPD_SEL
pin.
11.1.3.1 MAC Interface
The backplane segment MAC interface provides a connection to the repeater slice and backplane. In 100 Mbits/s
mode, the MAC interface is the nibble-wide MII interface running at 25 MHz as described in
IEEE
802.3u 1995,
section 22.
The backplane segment MAC interface looks like the PHY interface to the attached MAC device. In 10 Mbits/s
mode, the MAC interface is a serial NRZ interface running at 10 MHz or a nibble-wide MII interface at 2.5 MHz. The
NIB10
pin
(see Figure 20 on page 123)
selects the option of serial or nibble for the 10 Mbits/s MAC port.
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