
230
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
17 Key and Lamp Controller (KLC)
(continued)
17.3.4 KLC Interrupt Register
The
KLC interrupt register
contains the interrupt bits for KLC events. Writing a 1 to the corresponding bit will clear
the register. Writing a 0 will hold the current state. For a software reset (setting
RESET
in
Table 202 on page 229
),
this register will be left unchanged.
Table 205. KLC Interrupt Register
17.3.5 KLC Interrupt Enable Register
The
KLC interrupt enable register
allows masking of the three types of KLC interrupts. Writing a 1 to the corre-
sponding bit will clear the register. If an interrupt event occurs, the enable bit must be set to 1 in order for the inter-
rupt to be asserted in the
KLC interrupt register
and the
PIC interrupt request status register
(see Table 26 on
page 51)
. For a software reset (setting
RESET
in
Table 202 on page 229
), this register will be left unchanged.
Table 206. KLC Interrupt Enable Register
Table 204. Key Scan Status Register
Address 0xE000 D140, Read-Only
5
4
K_ROW
bit 2 (MSB)
bit 1
Bit #
Name
KEYPRESS SWHOOK
7
6
3
2
1
0
ON/OFF
K_ROW
K_ROW
bit 0 (LSB)
Description
K_COL
bit 2 (MSB)
K_COL
bit 1
K_COL
bit 0 (LSB)
Bit #
7
6
5
4
3
2
1
0
Name
KEYPRESS
SWHOOKON/OFF
K_ROW bit 2
K_ROW bit 1
K_ROW bit 0
K_COL bit 2
K_COL bit 1
K_COL bit 0
1 = key press; 0 = no key press.
Switch hook on/off.
Press key row number (MSB).
Press key row number.
Press key row number (LSB).
Press column row number (MSB).
Press column row number.
Press column row number (LSB).
Address 0xE000 D180
2
SWHK
Bit #
Name
Bit #
31:3
31:3
1
0
Reserved
Name
Reserved
SWHK
KEYR
KEYP
KEYR
KEYP
Description
Reserved.
Switch hook status change interrupt.
Key release interrupt.
Key press interrupt.
2
1
0
Address 0xE000 D1C0
2
SWHRE
Bit #
Name
Bit #
31:3
31:3
1
0
Reserved
Name
Reserved
SWHRE
KEYRE
KEYPE
KEYRE
Description
KEYPE
Reserved.
Switch hook status change interrupt enable.
Key release interrupt enable.
Key press interrupt enable.
2
1
0