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參數(shù)資料
| 型號： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁數(shù)： | 105/248頁 |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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Agere Systems Inc.
103
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
10 Ethernet 10/100 MAC
(continued)
10.3 MAC Transmitter
The transmit path consists of a 32x32 FIFO and transmit state machine.The programmer initiates a packet trans-
mission by first setting up the DMA to transfer packet data from memory to the transmit FIFO, excluding the pream-
ble,
SFD
, and
CRC
. The
START
bit
(see Table 95 on page 116)
is asserted and packet byte count is loaded into the
MAC controller transmit start register
(see Table 95 on page 116)
. It is the responsibility of the host system to
keep the transmit FIFO from underrunning.
In half-duplex mode, the MAC handles the collisions in accordance with
IEEE
802.3u. The MAC controller pre-
serves the first 64 bytes of data in the transmit FIFO so that, if there is a collision during the transmission of these
bytes, the MAC can retransmit the frame without the host system having to reload the FIFO. If a collision occurs
after 64 bytes have been transmitted, the transmission is aborted due to a late collision and an interrupt is gener-
ated if it is not masked.
The
CRC
is automatically appended at the end of the data packet and transmitted. An interrupt will be generated at
the end of a packet transmission to notify the processor about the successful or unsuccessful packet transmission.
If the interrupt is masked, then the host should monitor the MAC
transmit status register
(see Table 96 on page
116)
to determine when the transmitter is finished with the packet transmission.
10.4 MAC Receiver
The programmer sets up the IPT_
ARM
to receive Ethernet packets by programming the
MAC controller setup
register
(see Table 78 on page 106)
and address matching registers to determine which packets to accept and to
set up the circular input buffer in the IPT_
ARM
DMA block. If the receiver is enabled the incoming packets are
accepted and stored if they match the receive criteria.
The MAC can operate in a hardware flow control environment. When operating in full-duplex mode, if a pause
frame is received, the MAC controller waits for the time the sender wishes the MAC not to transmit. In addition, the
MAC controller also monitors the presence of VLAN type1 and type2 fields. If one of them is present, the maximum
legal frame length is extended.
An interrupt will be generated (if enabled) on a successful or unsuccessful packet reception and the status and
byte count of the received packet will be placed in the receive control FIFO. This information can be used by the
programmer to determine the amount of data written into the DMA input circular buffer and to determine the validity
of this data.
10.4.1 Address Matching Registers
The IPT_
ARM
has the capability of storing only those packets that meet predefined destination address criteria
programmed in 32 pairs of address match memory locations. Address match memory location 0 (memory loca-
tions 0XE001 0B00 and 0XE001 0B04) should be programmed with the endpoint's MAC address (the low-order 32
bits of the MAC address go in 0XE001 0B00 and the high-order 16 bits go in the least significant 16 bits of
0XE001 0B04). When the MAC receiver is not in promiscuous mode (
PROMM
= 0), received unicast packets will
only be written to the MAC receive FIFO if their destination addresses match the 48-bit value stored in address
match memory location 0.
Address match memory locations 1 to 31 (locations 0XE001 0B08 to 0XE001 0BFC) can be used to store up to
31 multicast addresses. These locations are paired in the same way that address match memory location 1 is; the
low-order 32 bits of the multicast address go in the first memory location of the pair and the high-order 16 bits go in
the least significant 16 bits of the second memory location of the pair. When the MAC receiver is not in the store-all
multicast packets
mode (
SAMUL
= 0,
see Table 78 on page 106
), received multicast packets will only be written to
the MAC receive FIFO if their destination addresses match one of the thirty-one 48-bit values.
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相關(guān)代理商/技術(shù)參數(shù) |
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| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302B | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302F | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303ABNAD | 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light) |
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