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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話(huà)高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 96/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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94
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
8 External Memory Interface (EMI)
(continued)
8.8 Signals
The EMI controls all the signals needed to access external devices. For transactions that are larger than the width
of the device, the EMI creates multiple accesses to read from or write to the device. For example, a 32-bit read from
an 8-bit device requires four read accesses. SDRAM, FLASH, and SRAMs share the same address and data bus.
8.8.1 Address, A[23:0]
For
FLASH_CS
,
CS1
,
CS2
, and
CS3
devices, the address bus signals
A[23:0]
define the address of the least sig-
nificant byte transferred during a memory cycle. The address becomes valid during phase 1 of the first cycle of an
access and remains valid until phase 1 of first cycle of the next access.
Note:
For FLASH and SRAM accesses,
A[23:0]
is used to access memory in units of bytes. If a 16-bit wide SRAM/
FLASH memory device is used,
A[1]
should be connected to the least significant address input pin of the
memory device. For 8-bit wide FLASH/SRAM devices,
A[0]
should be connected to the least significant
address input.
8.8.2 Data, D[15:0]
Data bus signals
D[15:0]
are bidirectional signals that transfer data to and from the chip. Use of the upper 8 bits of
the data bus is controlled on a per-device basis by
BS
(bit 6) of the
chip select configuration register
.
Note:
The program memory that is accessed by
FLASH_CS
always uses a 16-bit data bus. During a read access,
the data on the data bus is latched at the end of phase 1 of the last active cycle of the access. For a write
access, the data becomes valid during phase 1 of the second cycle of the access. If there is no valid transac-
tion on the EMI, the data bus stays in input mode.
8.8.3 Byte Enable, BE1N
BE1N
is used as a byte write enable for 16-bit devices that use byte enables. This signal is active-low and goes
active when an odd byte is to be written. The
UBE
bit (bit 13) of the
chip select configuration register
must be
set to 1 before attempting byte writes to 16-bit devices.
8.8.4 Read/Write Signals, RDN, WRN
RDN
and
WRN
are active-low signals that indicate whether a read or a write access is taking place. During a read
access,
RDN
goes low and
WRN
stays high. During a write access,
RDN
stays high am
WRN
goes low. If the EMI
flash is not being accessed,
RDN
and
WRN
stay high.
8.8.5 Chip Selects, FLASH_CS, CS1, CS2, CS3
The chip select signals
FLASH_CS
,
CS1
,
CS2
, and
CS3
indicate which of the external devices is accessed. The
appropriate chip select becomes active during phase 1 of the first cycle of an access if no setup cycle is used and
goes inactive after the last active cycle of the access.
FLASH_CS
is active-low.
CS1
,
CS2
, and
CS3
have program-
mable polarities and are active-low at reset.
8.8.6 External WAIT, EXWAIT
This signal can be driven by the external device to add additional wait-states to the memory access cycle, if
required. The use of the
EXWAIT
signal by a particular device is enabled by setting the
WT
bit (bit 8) of the appro-
priate
chip select configuration register
. The polarity of
EXWAIT
is programmable, and is determined by the
WP
bit (bit 0) of the
options register
;
see Table 65 on page 89
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| T8302A | 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302B | 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302F | 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303A | 制造商:MOLEX 制造商全稱(chēng):Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303ABNAD | 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light) |
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