
Agere Systems Inc.
95
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
8 External Memory Interface (EMI)
(continued)
8.8.7 EMI SDRAM, Synchronous DRAM Memory Interface
The EMI SDRAM interface can support one 16-bit wide synchronous DRAM device. SDRAM devices of other
widths (8-bit/4-bit) are not supported. Device sizes up to 256 Mbits are supported. The SDRAM's chip select
should be tied off to active.
8.8.8 SDRAM Address Functionality
Pins
A[14:0]
are used to output the row/column/bank address of the SDRAM location being accessed. Pins
A[23:15]
are not used during an SDRAM access. The output on these pins depends upon the type of SDRAM
access cycle, e.g., when used with a 64 Mbit 16-bit wide SDRAM device.
8.8.9 SDRAM Clock, SDRCK
This is the clock output that should be connected to the SDRAM. This runs at the same frequency as the IPT_
ARM
system clock.
8.8.10 SDRASN, SDCASN, SDWEN
SDRAM row address strobe (
SDRASN
), column address strobe (
SDCASN
), and write enable (
SDWEN
) are stan-
dard SDRAM interface signals. The combination of these three outputs is used to indicate the type of command
that is to be performed on SDRAM.
8.8.11 SDUDQM, SDLDQM
SDUDQM
and
SDLDQM
are SDRAM upper byte enable and lower data byte enable, respectively. In read mode
SDUDQM/SDLDQM
go low to turn on the SDRAM's output buffers. In write mode,
SDUDQM/SDLDQM
go low to
allow the corresponding byte to be written.
Note:
Care should be taken to have the shortest possible routes on the board, and to avoid excessive loading
(>15 pF) for all the EMI pins.
Table 71. SDRAM Access Cycles, Using a 64 Mbit SDRAM
SDRAM Command Cycle
Row address strobe (
RAS
)
Column address strobe (
CAS
)
Precharge
Address Pins
A[13: 0]
= row address, where
A[13:12]
= bank select.
A[7:0]
= column address.
A[10]
= precharge mode.
If
A[10]
= 1, all banks are precharged.
If
A[10]
= 0, only the bank selected by the bank select signals on the
SDRAM are precharged.