Table of Contents
(continued)
Tables
Page
12
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
Table 101. MAC Transmitted Multiple Collision Counter ......................................................................................119
Table 102. MAC Excess Collision Counter ...........................................................................................................119
Table 103. MAC Packet Deferred Counter ...........................................................................................................119
Table 104. MAC Controller Receive Control Register ..........................................................................................119
Table 105. MAC FIFO Status Register .................................................................................................................120
Table 106. MAC Controller Interrupt Status Register ...........................................................................................120
Table 107. MII MAC I/O Signals ...........................................................................................................................121
Table 108. DMA Interface Signals .......................................................................................................................122
Table 109. Repeater Slice
ARM
Interface ............................................................................................................129
Table 110. Repeater Slice Interface .....................................................................................................................129
Table 111. Repeater Slice Input Clocks ...............................................................................................................131
Table 112. Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B .......................................................132
Table 113. Repeater Slice Register Map ..............................................................................................................133
Table 114. Global Maximum Frame Size Register ..............................................................................................134
Table 115. Global Configuration Register ...........................................................................................................135
Table 116. Port Control Registers for Port 0, 1 ....................................................................................................136
Table 117. Port Configuration Register 0 for Port 0, 1 .........................................................................................136
Table 118. Port Configuration Register 1, for Port 0, 1 ........................................................................................138
Table 119. Global Interrupt Enable Register ........................................................................................................139
Table 120. Global Interrupt Status Register ........................................................................................................140
Table 121. Global Port Status Register, for Port 0, 1 ...........................................................................................141
Table 122. MII/5-Bit Serial Interface Signals ........................................................................................................143
Table 123. 10/100 Mbits/s Twisted Pair (TP) Interface Signals ............................................................................145
Table 124. Status Signals .....................................................................................................................................146
Table 125. Clock and Reset Signals ....................................................................................................................146
Table 126. MII Management Frame Format .........................................................................................................147
Table 127. Summary of Management Registers (MR) .........................................................................................148
Table 128. MR0 Control Register Bit Description .................................................................................................149
Table 129. MR1 Status Register Bit Description ..................................................................................................150
Table 130. MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description ............................................................150
Table 131. MR4 Autonegotiation Advertisement Register Bit Description ...........................................................151
Table 132. MR5 Autonegotiation Link Partner Ability (Base Page) Register Bit Description ...............................151
Table 133. MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description ........................152
Table 134. MR6 Autonegotiation Expansion Register Bit Description ..................................................................152
Table 135. MR7 Next Page Transmit Register Bit Description .............................................................................153
Table 136. MR16 PCS Control Register Bit Description ......................................................................................153
Table 137. MR17 Autonegotiation (Read Register A) ..........................................................................................154
Table 138. MR18 Autonegotiation (Read Register B) ..........................................................................................154
Table 139. MR21 RXER Counter .........................................................................................................................155
Table 140. MR28 Device-Specific Register 1 (Status Register) Bit Description ...................................................155
Table 141. MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description ............................................156
Table 142. MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description ..............................................157
Table 143. MR31 Device-Specific Register 4 (Quick Status) Bit Description .......................................................158
Table 144. USB Operational Register Map ..........................................................................................................163
Table 145. Hc Revision Register ..........................................................................................................................163
Table 146. Hc Control Register ............................................................................................................................164
Table 147. Hc Command Status Register ............................................................................................................166
Table 148. Hc Interrupt Status Register ..............................................................................................................167
Table 149. Hc Interrupt Enable Register ..............................................................................................................169
Table 150. Hc Interrupt Disable Register ............................................................................................................170