50
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
5 Programmable Interrupt Controller (PIC)
(continued)
5.2 Programmable Interrupt Controller Registers
Table 25. Programmable Interrupt Controller Register Map
Register
Address
0xE000 1000
0xE000 1004
0xE000 1008
0xE000 100C
0xE000 1010
0xE000 1014
0xE000 1018
0xE000 101C
0xE000 1020
0xE000 1024
0xE000 1028
0xE000 102C
0xE000 1030
0xE000 1034
0xE000 1038
0xE000 103C
0xE000 1040
0xE000 1044
0xE000 1048
0xE000 104C
0xE000 1050
0xE000 1054—
0xE000 1090
0xE000 1094
0xE000 1098
0xE000 109C
0xE000 10A0
0xE000 10A4
0xE000 10A8—
0xE000 10AC
Interrupt request status register IRSR
(see Table 26 on page 51)
.
Reserved.
Interrupt request enable set register IRER (IRESR)
(see Table 27 on page 51)
.
Interrupt request enable clear register IRER (IRECR)
(see Table 27 on page 51)
.
Interrupt request soft register IRQSR
(see Table 28 on page 52)
.
Reserved.
Interrupt priority control register 1
(see Table 29 on page 52)
.
Interrupt priority control register 2.
Interrupt priority control register 3.
Interrupt priority control register 4.
Interrupt priority control register 5.
Interrupt priority control register 6.
Interrupt priority control register 7.
Interrupt priority control register 8.
Interrupt priority control register 9.
Interrupt priority control register 10.
Interrupt priority control register 11.
Interrupt priority control register 12.
Interrupt priority control register 13.
Interrupt priority control register 14.
Interrupt priority control register 15.
Reserved.
Interrupt in-service register ISR (ISRI)
(see Table 30 on page 53)
.
Interrupt in-service register ISR (ISRF)
(see Table 30 on page 53)
.
Interrupt request source clear register IRQESCR
(see Table 32 on page 54)
.
Interrupt priority enable set registers IPER (IPESR)
(see Table 33 on page 54)
.
Interrupt priority enable clear registers IPER (IPECR)
(see Table 33 on page 54)
.
External interrupt control registers
(see Table 34 on page 55)
.