Agere Systems Inc.
219
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
16 Parallel Peripheral Interface (PPI)
(continued)
Table 190. PPI Port Data Register
The
PPI port data register
can be accessed in the following two methods:
I
Direct reads and writes of the
PPI port data register
. Note that to write selected bits, a read-modify-write opera-
tion must be performed on the
PPI port data register
in order to avoid changing other bits.
I
Reads and writes of the
PPI port data clear register
and
PPI port data set register
. A read of either of these
registers has the same effect as a read of the
PPI port data register
. A write to the
PPI port data set register
writes a 1 to selected bits of the
PPI port data register
(those bits with a value of 1 during the write to the
PPI port data set register
). The other bits of the
PPI port data register
remain unchanged. A write to the
PPI port data clear register
writes a 0 to selected bits of the
PPI port data register
(those bits with a value of
1 during the write to the
PPI port data clear register
). The other bits of the
PPI port data register
remain
unchanged. The use of the
PPI port data set register
and
PPI port data clear register
allows writing selected
bits of the
PPI port data register
using only one operation.
16.3.1 PPI Interrupt Enable Register
The
PPI port interrupt enable register
selects which bits of the port cause the port interrupt to be generated. If a
bit in the register is 1 and the bit is configured as an input, the pin generates interrupts based on how it is config-
ured in the
PPI port polarity register
. On reset, bits of this register are set to 0.
Table 191. PPI Interrupt Enable Register
16.3.2 PPI Port Sense Register
The
PPI port sense register
configures general purpose outputs as open-drain or direct-drive. If a bit in the regis-
ter is 0, the corresponding output pin is direct-drive. If a bit in the register is 1, the output pin is open-drain.
If a PPI
bit is an input, the corresponding bit in the PPI port sense register must be set to 0.
Table 192
shows the format of
the
PPI port sense register
. On all resets, all bits in the register are cleared to 0.
Address 0xE000 6004
Bit #
Name
Bit #
31:16
15:
0
31:16
RSVD
15:
0
P[15:
0
]
Name
RSVD
P[15:
0
]
Description
Reserved.
Port data bits. Bits configured as outputs reflect the value previously written to the register.
Bits configured as inputs reflect the (possibly inverted) level on the input pin.
Address 0xE000 6008
Bit #
Name
Bit #
31:16
15:
0
31:16
RSVD
15:
0
PIE[15:
0
]
Name
RSVD
PIE[15:
0
]
Description
Reserved.
Interrupt enable bits. If a bit in the register is 1 and the bit is configured as an input, the pin
generates interrupts based on how it is configured in the
PPI port polarity register.