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參數(shù)資料
| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 60/248頁(yè) |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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58
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
6 Programmable Direct Memory Access (DMA) Controller
(continued)
6.1.2 DMA Mode 0. Memory-to-Memory in Blocks of Burst Count Size
DMA mode 0 (memory-to-memory) is selected by setting
CMODE[2:0]
of the
DMA control register
(see Table 36
on page 62)
to 000.
Memory-to-memory transfers are set up as specified in
6.1.1 DMA Transfer Setup Procedure
.
Note:
When SDRAM is one of the memory sources, the DMA transfer may be less efficient than
ARM
controlled
transfers utilizing cache because only one word is transferred at a time.
I
When the start bit (
CS
) in the
DMA control register
(see Table 36 on page 62)
is set to 1, the DMA transfer will
start immediately in memory-to-memory mode as soon as the DMA ready signal is asserted.
I
The DMA will start to read, beginning at the address programmed in the
DMA source address register
(see
Table 37 on page 64)
. Transfers will be made to the address in the
DMA destination address register
(see
Table 39 on page 64)
, which is preset by writing to the
DMA preload destination start address registe
r
(see
Table 38 on page 64)
.
I
The number of items to be transferred is specified in the
DMA preload transfer count register
(see Table 40 on
page 65)
.
I
The DMA releases the bus to allow other masters access to it after each programmed burst by the number of
hold states (also programmed). Burst count (
BCNT[7:0]
) and hold count (
HCNT[7:0]
) are programmed in the
DMA burst and hold count register
(see Table 42 on page 66)
. Please note when using DMA to SSI,
BCNT[7:0]
must be set to 0.
I
Reads and writes in mode 0 (memory-to-memory) are performed with a data size programmed in the transfer
word size bits (
CTS
) in the
DMA control register
(see Table 36 on page 62)
. Available sizes are 8 bits, 16 bits,
or 32 bits.
Note:
Care should be taken when setting up memory-to-memory (mode 0) transfers to allow for other, needed bus
traffic.
6.1.3 Mode 1. Peripheral-to-Memory in Blocks of Burst Count Size
DMA mode 1 (peripheral-to-memory) is selected by setting
CMODE[2:0]
of the
DMA control register
(see Table
36 on page 62)
to 001.
Peripheral-to-memory transfers are set up as specified in
6.1.1 DMA Transfer Setup Procedure
.
I
In general, all transfers to/from peripherals should be 32-bit transfers. Valid data should be written into or read
from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer size.
The supported peripherals for DMA are Ethernet, SSI, IrDA, and UART. The
ARM
2DSP and DSP2
ARM
buffers
may also be treated as peripherals while using the software triggered DMA mode (
see Section 6.1.4.1 on page
60
).
I
When the start bit (
CS
) in the
DMA control register
(see Table 36 on page 62)
is set to 1, the DMA transfer will
start immediately in peripheral-to-memory mode (mode 1) as soon as the DMA ready signal is asserted. In the
mixed memory peripheral modes (modes 1 and 2), a software trigger (
SDRQ
) can be used to force the DMA to
see DMA ready.
Circular Buffer Mode (CBM):
Two transfer options are available in mode 1 and they are as follows:
I
The DMA will transfer until the transfer count, programmed through the
DMA preload transfer count register
(see Table 40 on page 65)
, is reached.
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