
Agere Systems Inc.
19
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
2 Pinout Information
(continued)
Ball
Signal
Description
I/O
Pull-Up/Down
Source/Sink
Current
External Memory Interface for FLASH and General Chip Select
FLASH chip select
Chip select 1 for SRAM
Chip select 2 for SRAM
Chip select 3 for SRAM
External Memory Interface SDRAM Control Signals
Row address strobe, active-low
Column address strobe, active-low
External WAIT pin
External interrupt input #1
External interrupt input #2
Write enable
SDRAM clock
SDLDQM is lower data byte enable
SDUDQM is upper byte enable
Read strobe
Write strobe
Byte enable
Common External Memory Interface
EMI data bus bit 15 (MSB)
EMI data bus bit 14
EMI data bus bit 13
EMI data bus bit 12
EMI data bus bit 11
EMI data bus bit 10
EMI data bus bit 9
EMI data bus bit 8
EMI data bus bit 7
EMI data bus bit 6
EMI data bus bit 5
EMI data bus bit 4
EMI data bus bit 3
EMI data bus bit 2
EMI data bus bit 1
EMI data bus bit 0 (LSB)
EMI address bus bit 23 (MSB)
EMI address bus bit 22
EMI address bus bit 21
EMI address bus bit 20
EMI address bus bit 19
EMI address bus bit 18
B11
A10
B10
C10
FLASH_CS
CS1
CS2
CS3
O
O
O
O
—
—
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
D9
A8
A9
B9
C9
B8
C8
A7
B7
C11
A11
D10
SDRASN
SDCASN
EXWAIT
EXINT1
EXINT2
SDWEN
SDRCK
SDLDQM
SDUDQM
RDN
WRN
BE1N
O
O
I
I
*
I
*
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
A6
C7
B6
A5
D7
C6
B5
A4
C5
B4
A3
D5
C4
B3
B2
A2
A19
B18
B17
C17
D16
A18
D [15]
D [14]
D [13]
D [12]
D [11]
D [10]
D [9]
D [8]
D [7]
D [6]
D [5]
D [4]
D [3]
D [2]
D [1]
D [0]
A[23]
A[22]
A[21]
A[20]
A[19]
A[18]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
50 k
pull-up
—
—
—
—
—
—
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
7 ma/7 ma
*Schmitt trigger input.
Table 1. PBGA-272 Package
(continued)