62
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
6 Programmable Direct Memory Access (DMA) Controller
(continued)
6.2.1 DMA Control Registers for Channels [0:3]
The
DMA control registers
programs different modes of DMA transfers. Table 36 shows the format of the
DMA
control registers
.
Table 36. DMA Control Registers for Channels [0:3]
Addresses, 0 (00xE000 2000), 1 (0xE000 2004), 2 (0xE000 2008), 3 (0xE000 200C)
31:15
14:12
11
RSVD
PS[2:0]
CBM
5:4
3
2
CTS[1:0]
RSVD
CIS
Name
RSVD
Reserved.
PS[2:0]
DMA peripheral select. DMA peripheral select bit encoding.
Bit #
Name
Bit #
Name
Bit #
31:15
14:12
10:8
7
6
CMODE[2:0]
1
CID
Description
SDRQ_E
0
CS
SDRQ
—
—
000
001
010
011
100:111 Reserved
Ethernet
IRDA
UART
SSI*
These hardware ready selects are only valid when
SDRQ_E = 0
.
Reset value = 000.
* Must have
FAST_CLEAR
set for DMA from SSI. Burst count should be set to 1 (pro-
grammed as 0) for DMA to SSI.
Circular buffer mode. Used only for peripheral-to-memory transfer mode, (mode1).
CBM
is
ignored in other modes. A
CH_DONEx
interrupt will not be generated when
CBM
is active.
11
CBM
If set to 1,
CBM
is enabled.
If set to 0,
CMB
is disabled.
Note: CBM
should not be used in conjunction with software trigger mode, since there is no
mechanism to ensure an endless supply of data. For example, once a peripheral's
FIFO is emptied, the data will be unknown.
Reset value = 0.
10:8
CMODE[2:0] Channel mode.
000
001
010
011:111 Reserved
Memory-to-memory (mode 0)
Peripheral-to-memory (mode 1)
Memory-to-peripheral (mode 2)
Reset value = 000
Software DMA request enable. Setting this bit to 1 will select
SDRQ
as the DMA request
signal instead of the
DRQ
input from the peripheral. Valid only for peripheral-to-memory
(mode 1) and memory-to-peripheral modes (mode 2).
7
SDRQ_E
Reset value = 0.
Software trigger DMA request. Setting this bit to 1 will trigger the DMA transfer in periph-
eral-to-memory (mode 1) and memory-to-peripheral modes (mode 2), when
SDRQ_E
= 1.
This bit is automatically cleared by hardware when the transfer is completed.
6
SDRQ
Reset value = 0.