
Agere Systems Inc.
203
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
15 Synchronous Serial Interface (SSI)
(continued)
15.2 SSI Registers
The SSI unit has five programmable registers. The
SSI data register
is used for writing the 8-bit byte to be trans-
mitted and for reading the received 8-bit byte.
SSI control registers
1
and
2
enable and configure the SSI for
serial communication in the desired mode. The
SSI interrupt register
and the
SSI interrupt enable register
dis-
play and enable interrupts, respectively. Table 181 below shows the register map of the SSI.
Table 181. SSI Register Map
15.2.1 SSI Data Register
The
SSI data register
contains the transmitted and received data bytes. The data byte that is transmitted is written
in the low-order byte of the
SSI data register
. The
SSI data register
is single buffered on the transmit side and
serves as the shift register for clocking out the bits with
SCK
.
The
SSI data register
is double buffered on the receive side. If all 8 bits are shifted in, the received data is copied
to a buffer register. The processor reads the contents of this register to determine the received word. Double buff-
ering on the receive side allows a new data byte to be shifted in while the previous one is read.
If in slave mode, the SSI uses the
SCK
pin to shift the
SSI data register
. While in master mode, it uses its internal
version of
SCK
.
For cases where
SPHA
= 1 and
SSN
is kept low between transfers, it is necessary to write bit
SSNEN
to 0
(in
SSI control register 1
) before writing the slave’s
SSI data register
.
Table 182. SSI Data Register
On reset, all
SSI data register
bits are set to 0.
Register
Address
0xE000 4000
0xE000 4004
0xE000 4008
0xE000 4010
0xE000 4014
SSI data register
(see Table 182 on page 203)
.
SSI control register 1
(see Table 183 on page 204)
.
SSI control register 2
(see Table 185 on page 206)
.
SSI interrupt register
(see Table 186 on page 206)
.
SSI interrupt enable register
(see Table 187 on page 207)
.
Address 0xE000 4000
Bit #
Name
Bit #
31:8
7:0
31:8
RSVD
7:0
TDWR
Name
RSVD
TDWR
Description
Reserved. Must be written with zeros.
Transmit/receive data. Transmit data on write, receive data on read.