
140
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.5.7 Global Interrupt Status Register
The
global interrupt enable register
is used to disable/enable a particular bit in the
global interrupt status reg-
ister.
If any bit of the
global interrupt status register
is set and the corresponding
global interrupt enable regis-
ter
bit is enabled, the device will drive the repeater interrupt. Reading the
global interrupt status register
does
not clear the interrupt. The interrupt condition will persist unless the processor writes a 1 to the corresponding bit in
the
global interrupt status register
. The processor must decide the priority of simultaneous interrupt conditions.
This register will default to the values in parenthesis after reset.
Table 120. Global Interrupt Status Register
Address 0xE001 2188
13, 5
SM1
SM0
Bit #
Name
31:16
RSVD
15, 7
ISO1
ISO0
State on
RST
(0)
(1)
(1)
(1)
(0)
—
14, 6
CLIS1
CLIS0
12, 8, 0
RSVD
11, 3
10, 2
VLE1
VLE0
9, 1
CAS1
CAS0
PHY_INT1
PHY_INT0
Bit #
Name
Description
31:16
15
14
13
12
11
RSVD
ISO1
CLIS1
SM1
RSVD
PHY_INT1
Reserved.
Isolation status.
Change in isolation status of port 1.
Link integrity status.
Change in link integrity status of port 1.
Port 1 error interrupt.
Symbol error interrupt setting register of port 1.
Reserved.
PHY1 interrupt status.
These interrupts are coming from PHY1. Even if the
repeater is in bypass mode, all the registers will be active and interrupt condi-
tion on PHY could be read from this register.
Very long event 1. Very long event interrupt setting register of port 1.
CAS1 interrupt setting register.
Change in autopartitioning status of port 1.
Reserved.
Isolation status.
Change in isolation status of port 0.
Link integrity status.
Change in link integrity status of port 0.
Port 2 error interrupt.
Symbol error interrupt setting register of port 0.
Reserved.
PHY0 interrupt status.
These interrupts are coming from PHY0. Even if the
repeater is in bypass mode all the registers will be active and interrupt condi-
tion on PHY could be read from this register.
Very long event 0.
Very long event interrupt setting register of port 0.
CAS0 interrupt setting register. Change in autopartitioning status of port 0.
Reserved.
10
9
8
7
6
5
4
3
VLE1
CAS1
RSVD
ISO0
CLIS0
SM0
RSVD
PHY_INT0
(1)
(1)
(0)
(1)
(1)
(1)
—
—
2
1
0
VLE0
CAS0
RSVD
(1)
(1)
(0)