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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁數(shù)： | 190/248頁 |
| 文件大?。?/td> | 7321K |
| 代理商： | T8302 |
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188
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
14 IrDA_ACC and UART_ACC
(continued)
14.1.1 Transmit and Receive Operation
In order to transmit data on the transmit line Tx, the
baud rate register
(see Table 170 on page 190)
is set, the
sample mode field of the
mode control register
(see Table 176 on page 193)
is set, the
transmitter control reg-
ister
is set
(see Table 175 on page 193)
, and then data is written into the transmitter FIFO. The data from the trans-
mitter FIFO is transferred to the
transmitter shift register
. A start bit is generated and then the data is shifted to
the output one bit at a time at the rate programmed in the
baud rate register
and the sample mode field of the
mode control register
. The data transmitted is synchronized to the baud rate generator so the width of the start bit
does not vary. The optional parity bit is then generated, followed by stop bit(s).
To receive serial data from the
Rx
input pin, set the baud rate and the
receiver control register
(see Table 173 on
page 192)
. When a start bit is detected, the data on the
Rx
line is shifted into the
receiver shift register
. This is
done by delaying one-half bit time and then sampling each data bit in the center of its ideal bit time. There is some
error when data is sampled if the baud rate counter does not match the baud rate exactly. The error introduced is
determined by the values programmed in the
baud rate register
and the sample mode field of the
mode control
register
. After shifting one character and the optional parity bit into the
receiver shift register
, the data is tested
for a parity error and the data is transferred to the receiver FIFO. If the controller detects receive errors, it sets
appropriate error bits in the
FIFO status register
(see Table 172 on page 191)
and generates an interrupt if the
ACC interrupt enable register
(see Table 180 on page 196)
was set to enable the corresponding interrupt.
A single interrupt line for each ACC is connected to the interrupt controller. When the
ARM
receives an interrupt
from one of the ACCs, the interrupt type is read from the respective
ACC’s
interrupt
register
.
14.1.2 Transfer Operating Modes
The ACC operates in several modes. There are 8 or 9 bits of data followed by optional parity bits. The receiver and
transmitter
can
operate in different parity modes but use the same number of data bits.
Table 167. ACC Transfer Modes
14.1.3 Programming the Baud Rate
The baud rate is programmed by setting values in two registers. Each bit period is divided into between 16 and
31 samples. This number is determined by adding 16 to the value set in
SM
of the
mode control register
(see
Table 176 on page 193)
. The sample period is determined by multiplying the input clock period by the value in the
baud rate register
+ 1. These two values, when multiplied together, are as close as possible to the ideal number of
clocks per bit for the desired baud rate.
The input clock for the ACCs on the IPT_
ARM
is the system clock. The maximum and default baud rate for the ACC
(IrDA and UART) transmit and receive data is 115.2 kHz. The input clock is divided by 500 to achieve this exact
baud rate. The number of sample clocks could be selected as 25, programmed as 9 (see bits 7:4
of the mode con-
trol register
in
Table 176 on page 193
), and the
baud rate register
could be selected as 19, to set the clock divider
to 20.
Mode: Bit 0 of Mode
Control Register
0
0
0
0
1
1
1
1
Parity Control: Bits[4:3] of
Transmitter/Receiver Control Register
00
01
10
11
00
01
10
11
Resulting Transfer
1 start, 8 data, 1 stop bit.
1 start, 8 data, 2 stop bits.
1 start, 8 data, 1 even parity, 1 stop bit.
1 start, 8 data, 1 odd parity, 1 stop bit.
1 start, 9 data, 1 stop bit.
1 start, 9 data, 2 stop bits.
1 start, 9 data, 1 even parity, 1 stop bit.
1 start,
9
data, 1 odd parity, 1 stop bit.
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