Agere Systems Inc.
187
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
14 IrDA_ACC and UART_ACC
There are two asynchronous communications controllers on the
IPT_
ARM
. The IrDA_ACC provides an IrDA infra-
red channel and the UART_ACC provides a connection to the expansion UART unit. A list of features of the two
ACC follows:
I
Full-duplex asynchronous communication.
I
Each ACC has 10 x 32 FIFOs for both receive and transmit.
I
One start bit, eight data bits, one optional ninth data bit, one optional parity bit, one stop bit.
I
Separate programmable baud rates.
I
Complete status reporting capabilities.
I
Support for DMA transfers.
I
IrDA input/output pulse formatter option (IrDA_ACC only).
I
Programmable IrDA output pulse to meet infrared transmitter and receiver timing requirements. (IrDA_ACC only.)
14.1 ACC Operation
As shown in Figure 22
below,
the function of the ACC is to convert incoming serial data on the receive line
(
IrDA_RX
, the RX inputs for IrDA_ACC, UART_ACC, respectively) to parallel data for the
ARM
, and convert parallel
data from the
ARM
to serial data on the transmit line (
IrDA_TX
, the TX outputs for IrDA_ACC
,
UART_ACC, respec-
tively). For each ACC the baud rate used to transmit and receive serial data is separately programmable using the
baud rate register
(see Table 170 on page 190)
and the sample mode field of the
mode control register
(see
Table 176 on page 193)
. The status of the transmitter and receiver FIFOs are used to generate interrupts.
The transmit and receive FIFOs are 10 bits wide by 32 entries deep. In 8-bit mode, data is stored in bit 7 through bit
0 (LSB). For 8-bit transfers, bits 9 (MSB) and 8 are always ignored on reads and written to 0. For 9-bit transfers,
bit 9 is used to control the extended character support.
5-8221 (F)
Figure 22. ACC Block Diagram
P
CONTROL
Rx FIFO
BAUD RATE
GENERATOR
Tx FIFO
IRQ
INTERRUPT
CONTROLLER
Rx SHIFT
REGISTER
Tx SHIFT
REGISTER
Rx
Tx
CLK