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| 型號(hào)： | T8302 |
| 英文描述： | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| 中文描述： | T8302因特網(wǎng)協(xié)議電話高級(jí)RISC機(jī)（ARM）的以太網(wǎng)使用IEEE 802.1q的服務(wù)質(zhì)量 |
| 文件頁(yè)數(shù)： | 130/248頁(yè) |
| 文件大小： | 7321K |
| 代理商： | T8302 |
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128
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
11 10/100 2-Port Repeater and Backplane Segment Controller
(continued)
11.3.4.4 Isolate on an Incorrect Clock Frequency
The repeater slice continuously checks the frequency of the clock received from the PHY (
RX_CLK
) using the
internally generated 50 MHz clock as a timebase. The result is reflected in the
DS
and
SM
bits in the
global port
status register
(see Table 121 on page 141)
. If the clock frequency is incorrect for the selected speed, the
repeater slice can be programmed to isolate the port from the repeater slice by setting the automatic speed mis-
match protection bit (
ASMP
) in the
port configuration register 1
to one
(see Table 118 on page 138)
.
11.3.4.5 Automatic Speed Mismatch Protection
Once the port has been isolated due to improper speed setting, the
ARM
can be alerted by an interrupt. When the
PHY returns to the selected speed, the port will return without
ARM
intervention. The speed mismatch circuit
comes up from reset for proper operation based on the
SPD_SEL
pin and assumes that the
RX_CLK
is correct.
The detection logic looks at the
RX_CLK
frequency (and not the data to determine if the clock is correct or not),
using the criteria listed below.
I
An
RX_CLK
with a period of 60 ns or less will be detected as being a valid 25 MHz clock.
I
An
RX_CLK
with a period of 80 ns or more will be detected as being a valid 10 MHz clock. This includes an
RX_CLK
at a dc value of 1 V or 0 V, and everything in between.
I
An
RX_CLK
with a period between 60 ns and 80 ns will result in the detection logic holding the indication for the
last clock speed that was detected.
There is a 620 ns window of hysteresis in switching between indicating a valid 25 MHz clock to invalid, and from
switching between indicating a valid 10 MHz clock to invalid. The repeater slice must see the newly detected clock
speed for at least 620 ns before the switch is made. If the detection logic indicates an invalid
RX_CLK
for the mode
selected and the mode is changed to agree with the detected clock, the invalid indication will change immediately
to valid.
Unpartition when LINK_STATUS = FAIL
In an
IEEE
802.3 compliant system, the partition state machine for the port will not reconnect once it has parti-
tioned unless
LINK_STATUS
= OK were being reported. However, it is often the case that a port has partitioned
because the attached cable has had its receive pair shorted to its transmit pair. In such a case, it is convenient to
have the partition clear as soon as the condition is corrected, i.e., the cable is removed. To clear the partition the
repeater slice has an optional mode where the partition state machine will be independent of
LINK_STATUS
=
FAIL. To enable this mode, the
ULF
bit in the
port configuration register 1
(see Table 118 on page 138)
must be
set to 1.
11.3.5 Carrier Integrity Monitor
The repeater slice contains a carrier integrity monitor (CIM) state machine that monitors
CARRIER_STATUS
,
RXERROR_STATUS
, and
LINK_STATUS
variables via the
CRS
,
RX_ER, LIS
, and
RX_DV
inputs from the PHY.
The CIM will isolate the port from the repeater if two consecutive false carriers (
CARRIER_STATUS
= ON with no
subsequent SSDs detected) or a single false carrier in excess of the 468—484 bit time
FALSE_CARRIER_TIMER
that is implemented are received.
In some applications, the PHY will contain the CIM state machine in which case the mode may be disabled by set-
ting
CIMD
in the
port configuration register 1
to one
(see Table 118 on page 138)
.
In cases where the PHY does not contain the CIM, it must supply the proper signaling for false carrier indication as
described in
IEEE
802.3u Table 22-2 (
RX_DV
= 0,
RX_ER
= 1,
RXD[3:0]
= 1110). The port will reconnect per
27.3.1.5.1 of
IEEE
802.3.
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| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302B | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302F | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8303ABNAD | 制造商:Arcolectric 功能描述:1 Pole Miniature push button(with light) |
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