
40
Agere Systems Inc.
T8302 Internet Protocol Telephone
Advanced RISC Machine (
ARM
)
Data Sheet
July 2001
4 Reset/Clock Management
(continued)
4.2.9 Reset Status (Control/Clear) Registers
The
reset status (control/clear) registers
identify the source of the last chip reset. The bit in the register corre-
sponding to the reset source is set to 1 and the other bits are cleared. Each bit is cleared by writing a 1 to the cor-
responding bit in the
reset status clear register
. Table 13 shows the format of the
reset status (control/clear)
register
.
Table 13. Reset Status (Control/Clear) Register
s
4.2.10 Reset Peripheral Control (Read, Clear, Set) Registers
The
reset peripheral control (read, clear, set) registers
provide the IPT_
ARM
with a mechanism for resetting an
individual peripheral without affecting other elements in the system. A 1 in a bit location corresponding to its
assigned peripheral holds the section in reset until the bit is cleared. Individual bits can be set by writing a 1 to the
corresponding bit location in the
reset peripheral control (set) register
. Values are read from the
reset periph-
eral (read) register
. Individual bits can be cleared by writing a 1 to the corresponding location in the
reset periph-
eral (clear) register
. Table 14 shows the format of the
reset peripheral control (read, clear, set) register
.
Address—Control 0xE000 0030, Clear 0xE000 0034
3
SFT
Bit #
Name
Bit #
31:4
3
31:4
RSVD
2
1
0
WR
POR
ER
Name
RSVD
SFT
Description
Reserved.
SFT identifies the last reset as a soft reset.
If 1, a soft reset has occurred.
If 0, the last reset was not a soft reset, or the bit was cleared.
Identifies the last reset as a warm reset (caused by the watchdog timer).
2
WR
If 1, a warm reset has occurred.
If 0, the last reset was not a warm reset, or the bit was cleared.
Identifies the last reset as a powerup reset.
1
POR
If 1, a powerup reset has occurred.
If 0, the last reset was not a powerup reset, or the bit was cleared.
Identifies the last reset as an external reset.
0
ER
If 1, an external reset has occurred.
If 0, the last reset was not an external reset, or the bit was cleared.